Dram Timing Control - DFI NS80-EA User Manual

3
Award BIOS Setup Utility
3.1.3.1 DRAM Clock/Timing Control
Move the cursor to this field and press <Enter>. The following
screen will appear.
The settings on the screen are for reference only. Your version may not be
identical to this one.

DRAM Timing Control

This field is used to select the timing of the DRAM.
By SPD
Manual
58
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Timing Control
X DRAM CAS Latency
X RAS Active Time (tRAS)
X RAS Precharge Time (tRP)
X RAS to CAS Delay (tRCD)
DRAM Addr/Cmd Rate
↑↓→← Move
Enter:Select
F5:Previous Values
The EEPROM on a DIMM has SPD (Serial
Presence Detect) data str ucture that stores
information about the module such as the memory
type, memory size, memory speed, etc. When this
option is selected, the system will run according to
the information in the EEPROM. This option is the
default setting because it provides the most stable
condition for the system. The "DRAM CAS
Latency" to "RAS to CAS Delay (tRCD)" fields will
show the default settings by SPD.
If you want a better performance for your system
other than the one "by SPD", select "Manual". Then
select the best option in the "DRAM CAS
Latency" to "RAS to CAS Delay (tRCD)" fields.
DRAM Clock/Timing Control
By SPD
2.5T
6T
3T
3T
Auto
+/-/PU/PD:Value F10:Save
F6:Fail-Safe Defaults
Item Help
Menu Level
ESC:Exit F1:General Help
F7:Optimized Defaults