Dram Timing - DFI LanParty LT P35 User Manual

DRAM Timing

Move the cursor to this field and press <Enter>. The following
screen will appear.
DLL Timing
Enhanced Data Transmitting
Enhanced Addressing
Channel 1 CLK Fine Delay
Channel 2 CLK Fine Delay
CAS Latency Time (tCL)
RAS# to CAS# Delay (tRCD)
RAS# Precharge (tRP)
Precharge Delay (tRAS)
All Precharge To Act
REF to ACT Delay (tRFC)
MCH ODT Latency
Write to PRE Delay (tWR)
Rank Write to Read (tWTR)
ACT to ACT Delay (tRRD)
Read To Write Delay (tRDWR)
Ranks Write to Write (tWRWR)
Ranks Read to Read (tRDRD)
Ranks Write to Read (tWRRD)
Read CAS# Precharge (tRTP)
All PRE to Refresh
↑↓→←
: Move Enter: Select
F5: Previous Values
The screen above list all the fields available in the DRAM Timing submenu, for ease
of reference in this manual. In the actual CMOS setup, you have to use the scroll
bar to view the fields. The settings on the screen are for reference only. Your ver-
sion may not be identical to this one.
DLL Timing
Refer to the following pages for more information on this submenu.
Enhance Data Transmitting
The options are Auto, Normal and Fast.
Enhance Addressing
The options are Auto, Normal and Fast.
Channel 1 CLK Fine Delay and Channel 2 CLK Fine Delay
The options are Auto, 1 and 2.
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Timing
Press Enter
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
8
6
6
5
Auto
Auto
+/-/PU/PD: Value F10: Save
F6: Fail-Safe Defaults
BIOS Setup
Item Help
Menu Level
ESC: Exit F1: General Help
F7: Optimized Defaults
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