Procedure 2: Signal Quality; Signal Quality Criteria - Intel Pentium II Application Note

Low-Power Module Memory Bus Simulation Methodology
6.2

Procedure 2: Signal Quality

Signal quality is simulated using the fast corner models because the fast edge rates will induce the
worst case overshoot and ringback. Overshoot is that part of the signal that transitions above V
below V
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crosses V
the signal that crosses V
Settling time is measured at V
to high transitions. For high to low transitions, settling time is measured at the last crossing of V
plus 10% of V
Table 5 outlines the signal quality criteria that are used to define constraints on overshoot and
undershoot. In the case of the 4-clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM
specification, the maximum instantaneous overshoot/undershoot is +/- 1.5 V, and the inputs may
overshoot beyond maximum V
inputs. For Low-Power Module/440BX memory interface signal quality conditions, the maximum
instantaneous overshoot/undershoot is +/- 1.6 V, and the inputs may overshoot beyond maximum
V (V + 5%) or undershoot below V
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Table 5.

Signal Quality Criteria

Driver
CLK Driver
440BX
CLK Driver
SDRAM
If there is a signal quality issue on a memory signal where the ringback crosses the threshold
regions (i.e., V
case, the flight time of a signal has to be measured at the last crossing of 2.0 V for the rising edge
and at the last crossing of 0.8 V for the falling edge. Figure 8 shows how to measure the flight time
when there is ringing.
14
when measured at the receiver pin. Ringback is measured as that part of the signal that
in the negative direction to its lowest part (for low to high transitions) and that part of
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in the positive direction to its highest part (for high to low transitions).
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minus 10% at the point the signal last crosses that voltage for low
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.
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(V
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Receiver Overshoot
≤ 1.5 V for ≤ 5 ns
SDRAM
≤ 1.5 V for ≤ 5 ns
SDRAM
≤ 1.6 V for ≤ 7 ns
440BX
≤ 1.6 V for ≤ 7 ns
440BX
, V ), then the maximum and minimum flight time has to be re-measured. In this
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+ 5%) or undershoot below V
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by 0.8 for 7.0 ns on the inputs.
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Undershoot
≤ 1.5 V for ≤ 5 ns
≤ 1.5 V for ≤ 5 ns
≤ 1.6 V for ≤ 7 ns
≤ 1.6 V for ≤ 7 ns
for 5 ns on the SDRAM
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Rise Time (min) Fall Time (min)
1 V/ns 1 V/ns
1 V/ns 1 V/ns
1 V/ns 1 V/ns
1 V/ns 1 V/ns
Application Note
or
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