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Pin
Name
I/O
no.
131
Reserved//CAS/PTJ[2]
O
132
VssQ
-
133
Reserved/PTJ[3]
O
134
VccQ
-
135
Reserved/PTJ[4]
O
136
Reserved/PTJ[5]
O
137
Vss
-
138
PTD[5]/CL1
O
139
Vcc
-
140
PTD[7]/DON
O
141
PTE[6]/M_DISP
O
142
PTE[3]/FLM
O
143
PTE[0]/TDO
O
144
PCC0RESET/DRACK0
O
145
PCC0DRV_/DACK0_
O
146
/WAIT
-
147
/RESETM
-
148
/ADTRG/PTH[5]
I
149
/IOIS16/PTG[7]
I
150
/ASEMD0
-
151
PTG[5]/ASEBRKAK_
152
PTG[4]
I
153
PCC0BVD2/PTG[3]/AUDATA[3]
I
154
PCC0BVD1/PTG[2]/AUDATA[2]
I
155
Vss
-
156
PCC0CD2/PTG[1]/AUDATA[1]
I
157
Vcc
-
158
PCC0CD1/PTG[0]/AUDATA[0]
I
159
VssQ
-
160
PTF[7]/PINT[15]/TRST_
I
161
VccQ
-
162
PTF[6]/PINT[14]/TMS
I
163
PTF[5]/PINT[13]/TDI
I
164
PTF[4]/PINT[12]/TCK
I
165
PTF[3]/PINT[11]/Reserved
I
166
PCCREG_/PTF[2]/Reserved
I
167
PCC0VS1_/PTF[1]/Reserved
I
168
PCC0VS2_/PTF[0]/Reserved
I
169
MD0
-
170
Vcc-PLL1
-
171
CAP1
-
172
Vss-PLL1
-
173
Vss-PLL2
-
174
CAP2
-
175
Vcc-PLL2
-
176
PCC0WAIT_/PTH[6]/AUDCK
I
177
Vss
-
178
Vcc
-
179
XTAL
-
180
EXTAL
-
181
LCD15/PTM[3]/PINT[10]
I
182
LCD14/PTM[2]/PINT[9]
I
183
LCD13/PTM[1]/PINT[8]
I
184
LCD12/PTM[0]
I
185
STATUS0/PTJ[6]
O
Function
CAS for SDRAM
VssQ
Output port (DAC Reset)
VccQ
Output port (SIO Reset)
Output port (DAC Mute)
Vss
LCD line clock
Vcc
LCD DISPLAY ON
LCD alternater
LCD frame line marker
JTAG (test data output)
DMA request acceptance
DMA acknowledge
Hardware wait request
Manual reset request
Analog A/D trigger
Not in use
Vss
Not in use
Vcc
Not in use
VssQ
Not in use
VccQ
Not in use
Clock mode setting
Power supply for Vcc_PLL1 - PLL1(1.9V)
External capacitance for CAP1 _ PLL1
Power supply for Vss_PLL1 _ PLL1(0V)
Power supply for Vss_PLL2 _ PLL2 (0V)
External capacitance for CAP2 _ PLL2
Power supply for Vcc_PLL2 _ PLL2 (1.9V)
Not in use
Vss
Vcc
Clock oscillator
External clock
Not in use
Input port (Flash ROM RY/BY)
Output port (Flash ROM write protect)
Pin
Name
I/O
no.
186
STATUS1/PTJ[7]
O
187
CL2/PTH[7]
O
188
VssQ
-
189
CKIO
-
190
VccQ
-
191
TxD0/SCPT[0]
O
192
SCK0/SCPT[1]
O
193
TxD_SIO/SCPT[2]
O
194
SIOMCLK/SCPT[3]
O
195
TxD2/SCPT[4]
O
196
SCK_SIO/SCPT[5]
O
197
SIOFSYNC/SCPT[6]
O
198
RxD0/SCPT[0]
I
199
RxD_SIO/SCPT[2]
I
200
Vss
-
201
RxD2/SCPT[4]
I
202
Vcc
-
203
SCPT[7]/CTS2_/IRQ5
I
204
LCD11/PTC[7]/PINT[3]
O
205
LCD10/PTC[6]/PINT[2]
O
206
LCD9/PTC[5]/PINT[1]
O
207
VssQ
-
208
LCD8/PTC[4]/PINT[0]
O
209
VccQ
-
210
LCD7/PTD[3]
O
211
LCD6/PTD[2]
O
212
LCD5/PTC[3]
O
213
LCD4/PTC[2]
O
214
LCD3/PTC[1]
O
215
LCD2/PTC[0]
O
216
LCD1/PTD[1]
O
217
LCD0/PTD[0]
O
218
DREQ0_/PTD[4]
I
219
LCK/UCLK/PTD[6]
I
220
/RESETP
-
221
CA
-
222
MD3
-
223
MD4
-
224
/Scan_testen
-
225
Avcc_USB
-
226
USB1_P
I/O
227
USB1_M
I/O
228
Avss_USB
-
229
USB2_P
I/O
230
USB2_M
I/O
231
Avcc_USB
-
232
Avss
-
233
AN[2]/PTL[2]
I
234
AN[3]/PTL[3]
I
235
AN[4]/PTL[4]
I
236
AN[5]/PTL[5]
I
237
Avcc
-
238
AN[6]/PTL[6]/DA[1]
I
239
AN[7]/PTL[7]/DA[0]
O
240
Avss
-
CPU: IC002
Function
Output port (Flash ROM ACC)
LCD clock output
VssQ
System clock input/output (for SDRAM)
VccQ
Output port for SCI
Not in use
Output port for SCI
Not in use
Receiving data 0
Not in use
Vss
Receiving data 2
Vcc
Not in use
Output port (PLG CLOCK ON/OFF)
Not in use
VssQ
Not in use
VccQ
LCD DATA7
LCD DATA6
LCD DATA5
LCD DATA4
LCD DATA3
LCD DATA2
LCD DATA1
LCD DATA0
DMA request
USB clock
Power on reset request
Hardware standby request
Bus width setting for area0
Test pin (fixed to 3.3V)
USB analog power supply (3.3V)
USB1 data input/output (+)
USB1 data input/output (-)
USB analog power supply (0V)
USB2 data input/output (+)
USB2 data input/output (-)
USB analog power supply (3.3V)
A/D analog power supply (0V)
AD converter input
A/D analog power supply (3.3V)
AD converter input
DA converter output (LCD contrast)
A/D analog power supply (0V)
SP2060
19
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