Possible Data Transfers On 32·Bit Bus; Read Cycle - Intel 80386 Reference Manual

LOCAL BUS INTERFACE
Table 3·3. Possible Data Transfers on 32·Bit Bus
Possible Data Transfers to 32·Bit Memory
Size Byte Enables
32 bits 3-2-1-0
24 bits 3-2-1
2-1-0
16 bits 3-2
2-1
1-0
8 bits
3
2
1
0
Figure 3·7 shows the steps required for a misaligned 32-bit transfer. In the first bus cycle,
the physical address crosses over into the next doubleword location, and BEO# and BEI# are
active. In the second bus cycle, the address is decremented to the previous doubleword, and
BE2# and BE3# are active. After the transfer, the data bits are automatically assembled in
the correct order.
Table 3-4 shows the sequence of bus cycles for all possible misaligned transfers. Even though
misaligned transfers are transparent to a program, they are slower than aligned transfers
and should thus be avoided.
Because the 80386 operates on only bytes, words, and doublewords, certain combinations of
BE3#-BEO# are never produced. For example, a bus cycle is never performed with only
BEO# and BE2# active because such a transfer would be an operation on two noncontiguous
bytes at the same time. A single 3-byte transfer will never occur, but a 3-byte transfer followed
or preceded by a I-byte transfer can occur for some misaligned doubleword transfers.
3.1.4
Read
Cycle
Read cycles are of two types: pipelined address cycles and non-pipelined address cycles. In
a non-pipelined address cycle, the address bus and bus status signals become valid during
the first eLK period of the cycle. In a pipelined address cycle, the address bus and bus status
signals are output before the beginning of cycle, in the previous bus cycle, to allow longer
memory access times. Pipelined address cycles are described in Section 3.1.6.
The timing for two non-pipelined address read cycles (one with and one without a wait state)
is shown in Figure 3-8.
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