FFIB PWB (FPGA Formatter Interface Board)
In the Cinema circuit, the FFIB PWB enters the video data of the VIDEO processor and the SOFTWARE processor
in the LVTTL (3.3V) 16-bit EVEN/ODD format. After passing through various functional processing of Item 1
below, the data are transmitted to the FSB in the LVDS (2.5V) 16-pair format.
In the bootstrapping mode, configuration control is also carried out for each FSB.
1. Electrical Interface
1-1. Intialzatopm
Signal Name
MB_RESETZ
MB_POWERGOOD
1-2. Main Data Interface
Signal Name
FCLK
O/E [R/G/B] (15:0)
O/E [R/G/B]_SIGN
O/E [R/G/B]_RSVD
MB_ACTDATA
MB_VSYNCZ
MB_HSYNCZ
MB_OLCATE
MB_OLACTO
MB_SYNCVAL
MB_3D_SYNC_IN
MB_3D_SYNC_OUT
"Confidential, Do Not Duplicate without written authorization from NEC."
CIRCUIT DESCRIPTION
PWC-4683
Description
Hardware Reset
Main Power Status
Description
Pixel Clock
Video Data, Odd/Even
Video Data, Odd/Even Sign
Video Data, Odd/Even Reserved
Input Active Data
Input Vertical Sync
Input Horizontal Sync
Input Overlay Active Even
Input Overlay Active Odd
Input Sync Vaild
3D Input Reference
3D Output reference
8-19
I/O
Type
I
LVTTL
I
LVTTL
I/O
Type
I
LVTTL
I
LVTTL
I
LVTTL
1
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
O
LVTTL