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S
S
UPER
ERVER 1027R-72RFTP User's Manual
Note: This is a general block diagram. Please see Chapter 5 for details.
Left WIO
Right WIO
x16
x8 CPU0
CPU0
PE3
PE2 [7..0]
x16 CPU1
PE3
x8 CPU1
PE1
x16 CPU1
PE2
SFP+ Conn + Cage
SFP+ Conn + Cage
Figure 1-1. Intel C602 Chipset:
System Block Diagram
to WIO
x16
x16
#1
#1
PE3
PE2
#2
#2
F
E
Socket 01
E5-2600 Series
Processor
P0
#1
#1
P1
#2
#2
CPU1
D
Socket 00
C
E5-2600 Series
Processor
PE3
PE2
x16
to WIO
x8 [7..0]
BMC57810S
x8 [15..8]
10G SFP+
Chipset
x8 Gen3
SAS2208
#1~#8
1-4
Powerville-2
x8
L1/L2
x4
#1
PE1
DMI
#2
H
CPU2
G
P1
#1
P0
#2
B
A
PE1
DMI
AT25321
SPI
DMI
SATA
PCH C602/C602J
SCU
PEG0
PEG1 [4:1]
PEG1_8
USB
LPC
PCI
USB
WPCM450
VGA BMC
VGA CONN
PHY1
RTL8201F
LAN
RJ45
RJ45
#1
#2
#1
#2
#1~#6
#7~#10
USB
0,1
2,3 4,5 6
REAR
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