Address Mapping; Port Allocations - Sun Microsystems Sun Blade 100 Service Manual

C.7

Address Mapping

This section provides the overview of address partitioning and software-visible
registers and their respective functionality. The physical address associated with
each of these registers is listed, along with a brief description of the register. For
further details on the description and functionality of the registers and chips, refer to
the respective chip specification.
Section C.7.1 "Port Allocations" on page C-18
Section C.7.2 "PCI Address Assignments" on page C-19
C.7.1

Port Allocations

The following table lists the system port allocations. The CPU divides the physical
address space among:
Main memory (DRAM)
PCI (which is further subdivided into the primary PCI bus (PCI-A) and the
secondary PCI bus (PCI-B bus) when the APB ASIC is used).
TABLE C-8
Address Range in
PA<40:0>
0x000.0000.0000 -
0x000.3FFF.FFFF
0x000.4000.0000 -
0x1FF.FFFF.FFFF
0x1FC.0000.0000 -
0x1FD.FFFF.FFFF
0x1FE.0000.0000 -
0x1FF.FFFF.FFFF
C-18 Sun Blade 100 Service Manual • October 2000
Port Allocations
Size
1 Gbyte
Do not use
8 Gbytes
8 Gbytes
Port Access Access Type
Main memory Cacheable
Undefined Cacheable
UPA graphics Non-cacheable
CPU IO Non-cacheable