MSI MS-6390 User Manual page 52

Chapter 3
Detect) EEPROM on the DRAM module. Setting to Yes enables DRAM
Frequency(MHz), DRAM CAS Latency, Bank Interleave, Row Precharge,
RAS Pulse, RAS to CAS and Burst Length automatically to be determined
by BIOS based on the configurations on the SPD. Selecting No allows
users to configure these fields manually.
DRAM Frequency(MHz)
The chipset supports synchronous and asynchronous mode
between host clock and DRAM clock frequency. Settings are:
HCLK
HCLK-33
HCLK+33
Auto
DRAM CAS Latency
This controls the timing delay (in clock cycles) before SDRAM
starts a read command after receiving it. Settings: 2, 2.5, 3, Auto.
2 (clocks) increases the system performance the most while 3
(clocks) provides the most stable performance.
Bank Interleave
This field enables or disables bank interleave for the installed
SDRAM. Disable the function if 16MB SDRAM is installed.
Settings: Disabled, Auto.
Row Precharge
This item controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for
the RAS to accumulate its charge before DRAM refresh, refresh
may be incomplete and DRAM may fail to retain data. This item
applies only when synchronous DRAM is installed in the system.
Available settings: 3T, 2T, Auto.
RAS Pulse
This setting allows you to select the number of clock cycles
The DRAM clock will be equal to the Host Clock.
The DRAM clock will be equal to the Host Clock
minus 33MHz. For example, if the Host Clock is
133MHz, the DRAM clock will be 100MH.
The DRAM clock will be equal to the Host Clock
plus 33MHz. For example, if the Host Clock is
100MHz, the DRAM clock will be 133MHz.
BIOS will automatically determine the clock
frequency.
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