Xerox 560 Reference Manual page 61

significance (FS), floating zero (FZ), and floating normalize
(FN) mode control bits, respectively (in the program status
words); however, if bit 11 is 0, the FR, FS, FZ, and FN
control bits are not affected. The functions of the floating-
point control bits are described in the section "Floating-
Point Arithmetic Instructions".
Affected: CC, FR, FS, FZ, FN
If (1)10
=
1, (1)24-27 -CC
If (1)10
= 0, CC is not affected.
Trap: Nonexistent in-
struction,
if
bit 0
is a
1.
If (1)11
=
I, (1)28-31 -FR, FR, FS, FZ, FN
If (1)11
=
0, FR, FS, FZ, and FN not affected.
Condition code settings,
if
(1)10
=
1:
2
3
4
(1)27
If LCFI is indirectly addressed, it is treated as a nonexistent
instruction, in whi ch case the computer unconditiona IIy
aborts execution of the instruction (at the time of operation
code decoding) and traps to location X'
40 '
with the condi-
tion code unchanged.
LCF
LOAD CONDITIONS AND FLOATING
CONTROL
(Byte index aiignment)
If
bit position 10 of the instruction word contains a 1,
LOAD CONDITIONS AND FLOATING CONTROL loads
bits 0 through 3 of the effective byte into the condition
code; however, if bit 10 is 0, the condition code is not
affected.
If
bit position 11 of the instruction word contains aI, LCF
loads bits 4 through 7 of the effective byte into the floating
round (FR), floating significance (FS), floating zero (FZ),
and floating normalize (FN) mode control bits, respectively;
however,
if
bit 11 is 0, the FR, FS, FZ, and FN control
bits are not affected. The functions of the floating-point
mode control bits are described in the section "Floating-
Point Arithmetic Instructions".
Affected: CC , FR, FS , FZ, FN
If (1)10
=
1, EB
O
_
3
-CC
If (I) 10
=
0,
CC not affected
If (I) 11
=
1, EB 4-7 -
FR, FS , FZ, FN
If (1)11
=
0, FR, FS, FZ, FN not affected
Condition code settings, if (1)10
=
1:
2
3 4
(EB)l
LVAW
LOAD VIRTUAL ADDRESS WORD
(Word index alignment)
H
34
I
R
I
X
I:
Reference;address
I
o
1 2 3 14 5 6 7 6 9 10 11 12 13 14 15 16 17 16 19120 21 22 23 24 25 26 27128 29 30 31
LOAD VIRTUAL ADDRESS WORD loads bit positions 15-31
of register R with the effective virtual word address of the
instruction whi Ie bit positions 0-14 of register R are cleared
to zero.
Affected: (R)
EVA - R
15
-
31
,
O-R
O
_
14
Note: Condition code is not affected by LVAW.
xw
EXCHANGE WORD
(Word index alignment)
EXCHANGE WORD exchanges the contents of register R
Affected: (R), (EWL), CC3, CC4
(R)-(EWL)
Condition code settings:
2 3 4 Result in R
0 0 Zero
-
-
0 Negative
0 Positive
STB
STORE BYTE
(Byte index alignment)
H
75
I
R
I
X
I:
Referenc~
address
I
o
1 2 314 5 6 78 9 1011 12 13 14 15 16 17 18 19120 21222324252627128293031
STORE BYTE stores the contents of bit positions 24-31 of
register R into the effective byte location.
Affected: (EBL)
(R)24-31 -EBL
Load/Store Instructions 55