Xerox 560 Reference Manual page 113

In the real extended addressing mode, a 20-bit address may
be used as a branch address via indexing or indirect ad-
dressing. If such a branch address, (A), is beyond the first
128Kofreal memory, the instruction at (A) will be executed,
but the next instruction address will be (A+1) in the original
128K block unless (A) contains a branch instruction. Note
that with this exception all instructions executed in the
real extended addressing mode must lie in the first 128K of
rea
I
memory.
EXU
EXECUTE
(word index alignment)
EXECUTE causes the basic processor to access the instruction
in the location pointed to by the effective address of EXU
and execute the subject instruction. The execution of the
subject instruction, including the processing of trap and
interrupt conditions, is performed exactly as if the subject
instruction were initially accessed instead of the EXU in-
struction. If the subject instruction is another EXU, the
basic processor executes the subject instruction pointed to
by the effective address of the second EXU as described
above. Such "chains" of EXECUTE instructions may be of
any length, and are processed (without affecting the updated
instruction address) until an instruction other than EXU is
encountered. After the final subject instruction is executed,
inc:for"rtit"ln Pypr"tit"ln nrt"lrpp,.lc;.
with thp. np.xt instruction in
... _ .. __ .. _-- ----------- r------_·
sequence after the initial EXU (unless the subject instruc-
tion is an LPSD or XPSD instruction, or is a branch instruc-
tion and the branch condition is satisfied).
If an interrupt activation occurs between the beginning of
an EXU instruction (or chain of EXU instructions) and the
last interruptible point in the subject instruction, the BP
processes the interrupt-servicing routine for the active
interrupt level and then returns program control to the EXU
instruction (or the initial instruction of a chain of EXU
instructions), which is started anew. Note that a program
is interruptible after every instruction access, including ac-
cesses made with the EXU instruction, and the interrupt-
ibility of the subject instruction is the same as the normal
interruptibility for that instruction.
If a trap condition occurs between the beginning of an EXU
instruction (or chain of EXU instructions) and the comple-
tion of the subject instruction, the basic processor traps to
the appropriate trap location. The instruction address stored
by the XPSD instruction in the trap location is the address
of the EXU instruction (or the initial instruction of a chain
of EXU instructions).
Affected: Determined by
subject instruction
T raps: Determined by
subject instruction
Condition code settings: Determined by subject instruction.
BCS
BRANCH ON CONDITIONS SET
(Word index alignment)
BRANCH ON CONDITIONS SET forms the logical product
(AND) of the R field of the instruction word and the current
condition code. If the logical product is nonzero, the
branch condition is satisfied and instruction execution pro-
ceeds with the instruction pointed to by the effective ad-
dress of the BCS instruction. However, if the logical prod-
uct is zero, the branch condition is unsatisfi ed and instruc-
tion execution then proceeds with the next instruction in
normal sequence.
Affected: (lA) if CC n R
f
0
If CC n (1)8_11/0, EVA 15 - 31 - I A
If CC n (1)8-11
=
0, IA not affected
If the R field of BCS is 0, the next instruction to be exe-
cuted after BCS is always the next instruction in ascending
sequence, thus effectively producing a "no operation
II
instruction.
BCR BRANCH ON CONDITIONS RESET
(Word index alignment)
BRANCH ON CONDITIONS RESET forms the logical prod-
uct (AND) of the R field of the instruction word and the
current condition code. If the logical product is zero, the
branch condition is satisfied and instruction execution then
proceeds with the instruction pointed to by the effective
address of the BCR instruction.
However, if the logical
product is nonzero, the branch condition is unsatisfied and
instruction execution then proceeds with the next instruc-
tion in normal sequence.
Affected: (IA) if CC n R
=
0
If CC n (1)8-11
=
0, EVA 15 _ 13 - IA
If CC n (1)8-11
10,
IA not affected
If the R field of BCR is 0, the next instruction to be exe-
cuted after BCR is always the instruction located at the
effective address of BCR, thus effectively producing a
"branch unconditionally" instruction.
Execute/Branch Instructions 107