Fixed-Point Arithmetic Instructions - Xerox 560 Reference Manual

R 1 R2 R3 Meaning
o
The effective virtual address of the AN LZ
instruction would have trapped because it was
either nonexistent, memory protected, or had
a parity error. The CCs are indeterminate
since the instruction to be analyzed may not
have been fetched {nonexistent memory}.
R(l0-31) contain the effective virtual address
of the AN LZ instruction aligned as a word
displacement.
If no trap condition occurs, ANLZ will execute normally
and return the effective address of the instruction analyzed.
Table 6 shows the instruction set as a 4 by 32 matrix {ar-
ranged as a function of the operation code}. This table also
shows how the instruction set is divided into six groups as
a function of the addressing type {delineated by heavy
lines}. For example, if the operation code of the analyzed
instruction is either X ' 02 1
,
X ' 20 ' , X ' 21 1
,
X ' 22 1
,
or X ' 23 1
,
then CCl is set to 1, CC2 is set to 0, CC3 is set to 0 {when
analyzed instruction specifies direct addressing}, and CC4
is set to
1.
The decimal equivalent of the condition code
setting for this group of immediate, word addressing type of
instructions is shown as a 9 within a circle. The decimal
equivalents of the condition code settings for the other
five groups are shown in the same manner. If the analyzed
instruction calls for indirect addressing, CC3 is always set
to a 1 and the decimal value of the condition code setting
shown in Table 6 should be increased by 2.
Affected: {R}, CC
r ___
-1·.L~_.
____ 1 ___
.1..1.- __ _
,",VIIUIIIUIi ....
vuc
:>ClllIll:;I:>;
2 3 4 Instruction addressing type
0 0
-
0 Byte
0 0 Immediate, byte
0
-
0 Halfword
0
-
0 Word
0 Immediate, word
-
0 Doubleword
-
0
-
Direct addressing {EWO = O}
-
Indi rect addressi ng {EWO
=
1}
INT INTERPRET
(Word index alignment)
INTERPRET loads bits 0-3 of the effective word into the
condi ti on code, loads bits 16-31 of the effecti ve word into
bit positions 16-31 of register Ru1 {and loads OIS into bit
positions 0-15 of register Rul, loads bits 4-15 of the
effective word into bit positions 20-31 of register R (and
clears the remaining bits of register R). If R is an odd value,
INT loads bits 0-3 of the effective word into the condition
code, loads bits 16-31 of the effective word into bit posi-
tions 16-31 of register R, and loads OIS into bit posi-
tions 0-15 of register R (bits 4-15 of the effective word are
ignored in this case).
Affected: {R}, (Rul), CC
EW
O
_
3
-CC
EW
4
_
15
_R
20
_
31
; 0 - R
O
-
19
EW 16-31- Rul 16 _ 31 ;0 _Rul 0 _ 15
Condition code settings:
2 3
4
{EW)l
Example 1, even R field value:
Before execution After execution
EW XI 12345678 1 XI 12345678 1
(R) xxxxxxxx
XI 00000234
1
(Ru 1)
=
xxxxxxxx X I 000056 78 1
CC xxx x 0001
FIXED-POINT ARITHMETIC INSTRUCTIONS
The fixed-point arithmetic instructions are:
Instruction Name Mnemonic
Add Immedi ate AI
Add Ha If word AH
Add Word
AW
Add Doubleword AD
Subtract Halfword SH
Subtract Word
SW
Subtract Doubleword
SD
Multiply Immediate
MI
Multiply Halfword
MH
Multiply Word
MW
Di vi de Ha If word
DH
Fixed-Point Arithmetic Instructions 59