Control Of The Interrupt System - Xerox 560 Reference Manual

is assumed to contain an XPSD or a PSS instruction that
transfers program control to a routine for servicing all
I/o
interrupts. The
I/o
routine should contain an ACK NOWL-
EDGE
I/o
INTERRUPT (AIO) instruction that identifies the
source and reason for the interrupt. (The AIO instruction is
discussed in Chapter 3 "Input/Output Instrudions".)
The control panel interrupt level is activated from the op-
erator1s console. This location normally contains an X PSD
or a PSS instruction. The operator can thus trigger this in-
terrupt level to initiate a specific routine.
The interrupt levels in the
I/o
group can be inhibited or
permitted by means of bit position 38 (II) of the PSWs.
If II is reset to zero, interrupt signals affecting the
I/o
group interrupt levels are allowed to interrupt the program
being executed. If the II bit is set to one, interrupt
signals in this group are inhibited from interrupting the
program.
EXTERNAL INTERRUPTS
A system can contain 4 optional groups of external inter-
rupt levels. The external override group, group 3, contains
the first 12 external interrupt levels. External groups 2,
4, and 5 each contain 12 external interrupt levels. (See
Table 2 and Figure 11.) External levels may be triggered
by external sources or via WD instructions, while internal
levels may be triggered by internal sources or via WD
instructions.
All external interrupt levels normally contain XPSD or PSS
instructions and can be inhibited or permitted by means of
the setting of bit position 39 (EI) of the program status words.
If EI contains a zero, external interrupts are allowed to in-
terrupt a program; if EI contains a one, all external inter-
rupts are inhibited from interrupting the program.
NUMBER OF INTERRUPT GROUPS
The 14 internal interrupt levels are standard in every system
and all external levels are optional. The addition of the
external groups (12 levels per group) raises the number of
interrupt levels to a maximum of 62.
CONTROL OF THE INTERRUPT SYSTEM
The system has two points of interrupt control. One point
of interrupt control is achieved by means of the interrupt
inhibit bits (CI, II, and EI) in the program status words (PSWs).
The basic processor is inhibited from interrupting a program
if the interrupt inhibit bit for a corresponding class of inter-
rupt levels is set to one, that is, no interrupt level in the
inhibited group can advance from the waiting state to the
active state, and the entire group is disabled (removed from
the interrupt recognition priority chain) • Consequently, a
waiting, enabled, interrupt level in an inhibited group does
not prevent a lower priority, waiting, enabled interrupt
level in an uninhibited group from interrupting the program.
However, if an interrupt group is inhibited while a level in
that group is in the active state, no lower priority interrupt
level can advance to the active state.
Note also this special case: When the processor detected
fault (PDF) flag is set to 1 (see "Processor Detected Faults Jl ,
later in this chapter), the processor fault, memory fault, and
count pulse interrupts are automatica lIy inhibited.
The second point of interrupt control is at the individual in-
terrupt level. The basic processor can interact with any
interrupt level by means of special modes of the RD and WD
instructions (described in Chapter 3, JlControl Instructions Jl ).
For this purpose, the interrupt levels are organized into the
following DIO address groups (see last two columns in
Table 2):
1. The 14 levels of internal interrupts (internal override
group, counter-equals-zero group, and
I/o
group) are
designated as group code 0 in bits 28-31 of the effec-
tive address of the RD or WD instruction.
2. The 12 levels of each group of external interrupts are
designated as group codes 2, 3, 4, and 5. That is,
external group 2 is designated group code 2, external
group 3 is designated group code 3, etc.
3. There is no group code 1.
The addressing of an individual interrupt level within its
DIO group of 12 or 14 is accomplished by an assigned selec-
tion bit within the low-order 16-bit positions of the R reg-
ister designated in the RD or WD instruction (see last
column in Table 2).
The WD instruction can individually arm, disarm, enable,
disable, or trigger (move to the active state) any interrupt
level. The RD instruction can determine which interrupt
levels within a selected DIO group are in the armed or
waiting state, waiting or active state, or are enabled.
TIME OF INTERRUPT OCCURRENCES
The basic processor permits an interrupt to occur during the
following time intervals (related to the execution cycle of
an instruction) provided the SCP basic processor (BP) sta-
tus indicators are either in the RUN or WAIT condition:
1. Between instructions an interrupt is permitted between
the completion of any instruction and the initiation of
the next instruction.
2. Between instruction initiations an interrupt is also per-
mitted to occur during the execution of the following
multiple-operand instructions:
MOVE BYTE STRING (MBS)
COMPARE BYTE STRING (CBS)
TRANSLATE BYTE STRING (TBS)
Centralized Interrupts 35