Xerox 560 Reference Manual page 118

memory control feature, CC2 and CC4 are both
set to 1
IS;
if
bit 9 of XPSD is a 1, the instruction
address of the new program status words is incre-
mented by 5.
2. CALL instructions - the following additional functions
are performed when XPSD is being executed as a re-
sult of a trap to location X'48', X'49'
i
X'4A', or
X'4B'.
a. The R field of the CA LL instruction causing the
trap is logica"y inclusively ORed into bit posi-
tions 0-3 (CC) of the new PSWs.
b.
If
bit position 9 of XPSD contains a 1, the R field
of the CALL instruction causing the trap is added
to the instruction address portion of the new PSWs.
3. Watchdog timer, parity error, or instruction exception
trap - the following additional functions are performed
when XPSD is being executed
a~
a result of a trap to
location X'46', X'4C', or X'4D', respectively.
a. The contents of TCC 1-4 are logically inclusively
ORed into bit positions 0-3 (CC) of the new PSWs.
b.
If
bit position 9 of XPSD contains a 1, the contents
of TCC 1-4 are added to the instruction address
portion of the new PSWs.
If
bit position 9 of XPSD contains a 0, the instruction ad-
dress portion of the new PSWs always remains at the value
established by the second effective doubleword. Bit posi-
tion 9 of XPSD is effective only
if
the instruction is being
executed as the result of a nonallowed operation, CALL
instruction watchdog timer, parity error, or instruction ex-
ception trap. Bit position 9 of XPSD must be coded with a
o
in all other cases; otherwise, the results of the XPSD
instruction are undefined.
The current program status words are stored in the doubl e-
word location pointed to by the effective address of XPSD
in the following form:
Program Status Words
The current program
status WOrds (as
iI
hjs~ra~ed
above) arE:
replaced by new program status words as described below.
1. The effective address of XPSD is incremented by 2 so
that it points to the next doubleword location. The
contents of the next doubl eword location are referred
to as the second effective doubleword, or ED2.
112 Control Instructions
2. Bits 0-35, 60, and 61 of the current program status
words are unconditionally replaced by bits 0-35, 60,
and610f the secondeffectivedoubleword. The affected
portions of the program status words are:
Bit
Position Designation Function
0-3 CC Condition code
4-7 FR,FS,FZ, Floating control
FN
8 MS Master/slave mode control
9
MM
Mapping mode control
10 DM Decimal arithmetic trap mask
11
AM Fixed-point arithmetic trap mask
15-31 IA Instruction address (real or virtual)
32-35 WK Write key
60
RA
Register altered
61 MA Mode altered
3. A logical inclusive OR is performed between bits 37
through 39 of the current program status words and
bits 37 through 390f the second effective doubleword.
Bit
Position Designation Function
37 CI Counter interrupt inhibit
38
II
I/O interrupt inhibit
39 EI External interrupt inhibit
If
any (or all) of bits 37, 38, or 39 of the second ef-
fective doubleword are O's, the corresponding bits in
the current program status words remain unchanged;
if
any (or all) of bits 37, 38, or 39 of the second effec-
tive doubl eword are 1
IS,
the corresponding bits in the
current program status words are set to 1 'so See "In-
terrupt System", Chapter 2, for a detailed discussion
of the interrupt inhibits.
4.
If
bit position 8 (LP) of XPSD contains a 1, bits 58
and 59 (register pointer) of the current program status
words are replaced by bits 58 and 59 of the second
effective doubieword; if bit 8 of XPSD is a 0, the cur-
rent register pointer value remains unchanged.
Affected: (EDL), (PSWs)
If
(1)10
=
1, trap or interrupt instructions only, effective
address is subject to current active addressing mode.