Dsps And The Peripheral Circuit; Reception Signal Path; Flow Of Audio Clock - Kenwood TS-990S Service Manual

TS-990S
8-2. DSPs (IC202 and IC300) and the Peripheral Cir-
cuit
There are two types of DSPs. The TXMRX-DSP (IC202)
is used for transmission processing, main band reception,
and RTTY/PSK31 encoding, and operates at an internal
core voltage of 1.2 V, external I/O voltage of 3.3 V, reference
clock frequency of 24.576MHz, and operating clock frequen-
cy of 331.776MHz. The SRX-DSP (IC300) is used for sub-
band reception and various signal path processing (except
for band scope and display processing and RTTY/PSK31
decoding), and operates at an internal core voltage of 1.2
V, external I/O voltage of 3.3 V, reference clock frequency of
24.576MHz, and operating clock frequency of 258.048MHz.
The SRX-DSP (IC300) supplies the BICK (SCLK96K)
a n d L R C K ( L R C K 9 6 K ) fo r a n M C L K f r e q u e n c y o f
24.576MHz and a sampling frequency (fs) of 96kHz to each
ADC and DAC. The Flip Flop (IC380) divides the SCLK96K
and LRCK96K to generate the BICK (SCLK48K) and LRCK
(LRCK48K) for an fs of 48kHz. The SCLK96K and LRCK96K
IC202
TXMRX-DSP
SCLK96K/
LRCK96K
SCLK48K/
LRCK48K
8-3. Reception Signal Path (IF Signal/FM Wave De-
tection to AF output)
The signal (MRIF) in FM or other modes output from the
CN137 on the RX unit (X55-313 A/2) is sent to the MRIF
connector (CN665) on the DSP unit (X53-453) and input into
the L channel of the ADC (IC398) through the active fi lters
(IC675 and IC667). The TXMRX-DSP processes the MRIF
signal sampled by the ADC at a sampling frequency (fs) of
96kHz.
The signal (SRIF) in FM or other modes output from the
CN600 on the TX-RX unit (X57-827 A/2) is sent to the SRIF
connector (CN670) on the DSP unit and input into the L
channel of the ADC (IC392) through the active fi lters (IC670
and IC678). The SRX-DSP processes the SRIF signal sam-
pled by the ADC at a sampling frequency (fs) of 96kHz.
The signal processed by each DSP is sent from the SRX-
DSP to the DAC (IC390) and converted to an AF signal at an
fs of 48kHz. The DAC outputs the SP1 signal for the L chan-
32
CIRCUIT DESCRIPTION
IC300 SRX-DSP
SCLK96K/ SCLK48K/
LRCK96K LRCK48K
SCLK96K
IC399
NAND
IC380
Flipflop
(Frequency devider)
LRCK96K
IC381
Buffer
SCLK48K
IC382
Buffer
LRCK48K
Fig. 36 Flow of audio clock
are supplied to the TXMRX-DSP (IC202) while the SCLK48K
and LRCK48K are supplied to the TXMRX-DSP and SRX-
DSP.
The Flash memories (IC203 and IC301) are used to store
each DSP program, and the Latch ICs (IC200 and IC201)
are used as an address decoder for the TXMRX-DSP use.
The buffer (IC302) is used for the 8-port expansion input for
the SRX-DSP. The SRS-DSP exchanges transmission and
reception data from the optical I/O (A650 and A651).
The main MCU serves as a host. Therefore, the DSP-
SubMCU (IC101) performs UART and SPI conversion in
order to enable communications between the host and each
DSP. The DAC (IC658) is connected to the DSP-SubMCU
to control the electronic volume ICs (IC664 and IC664) in
control of various functions, such as volume control, mute
control DSP reset release control, or boot control.
When the DSP-SubMCU is in SPI communication with
the TXMRX-DSP (IC202) and SRX-DSP (IC300), the DSP-
SubMCU serves as the master and each DSP serves as a
slave.
MCLK96K
IC392 ADC(SRIF/ANI,UANI)
IC397 DAC(TIF/MAGCV)
IC398 ADC(MRIF/MIC)
MCLK_1
SCLK_1
IC386 DAC(MUANO/SUANO)
IC388 DAC(SAGCV/SSCPI)
LRCK_1
IC391 DAC(MANO/SANO)
SCLK_2 IC385 DAC(BEEP/MSCPI)
IC389 ADC(MRECO/SRECO)
LRCK_2
IC390 DAC(SP1/SP2)
IC397 DAC(MRECI/SRECI)
nel and SP2 signal for the R channel.
The signal output from the DAC passes through the ac-
tive fi lter (IC650), and is converted to a certain voltage level
by the electronic volume ICs (IC664 and IC665). This signal
mixed with the BEEP signal and MIXSP signal in IC673,
and passes through the active fi lter (IC660 and IC661), and
is applied to the AF power amplifi ers (IC51 and IC52) and
headphone amplifi ers (IC50 and IC671).
The SP1 signal input into the AF power amplifi er is sent
as a built-in speaker output from CN50 after the signal pass-
es through the mute circuit. If an external SP1 is used, the
signal is sent from J50 (the built-in speaker and the external
SP1 cannot be used simultaneously.). The SP2 signal is sent
for an external SP2 from J51.
The SP1 signal (for the L channel) and SP2 signal (for
the R channel) signal input into the headphone amplifi er are
sent from CN667 and connected to the PHONES jack on the
front panel.
MCLK48K
IC383
Buffer
MCLK_2