Pc I/F Block (Overall) - Pioneer PDP-R03U Training Manual

PC/IF BLOCK DIAGRAM
12 CLR_ SW
7
9
10
5
1
3
MAIN _H
MAIN_VD
P C_R
18
PC _G
17
P C_B
MAI N_
29,3
0
MAI N_
25,2
6
MAI N_
21,2
2
12V->9V R eg
IC415 B A09FP
VIDEO SIGNAL
PEAK DETECTION
ACL_S IG
13,1
SUB _Y
4
9,10 SUB_ Cb
5,6 SUB_ Cr
V1 ADC
RT, RB SETTING
CIRCUIT
2
1
40.
PC _H 1B
P C_V
2B
P C_C
4B V0
Sync
Sel
1A
2A
IC411
74LCX157
4A
D
HV SEL -A /+B
12V->5VReg
IC7 PQ0 5TZ11
RIN2
GIN2
BIN2
RIN1
R V0
A/D
GIN1
G
Amp
BIN1
B
PLL
IC4
CXA3506R
ROUT
2
I C=CH2
GOUT
BOUT
OV0_CLP
5V->3.3V Reg
IC8 PQ2 0VZ11
AIN
BIN
V1
A/D
CIN
IC310
3.27V
RT
TLC57 33A
1.17V
RB
V1
PLL
About 60MHz
VCOOUT
IC328
TLC 2933IPW
PDP-R03U
Main Picture (green), Sub Picture (red), PC
input (brown), Processed output (purple)
X4
25MHz
1Y
OV0 _H
2Y OV0_V
4Y PC_ C3
CXA3506R
OV0_PDEN
VCO
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
SYNCIN1
SYNCIN2
HOLD
OV0_CLP
CLPIN
OV0_HSC2
DIVOUT
OVCLK(Max60MHz)
1/2C LK
8
RA[7..0]
8
RB[7..0]
8
GA[7..0]
8
GB[7..0]
8
BA[7..0]
8
BB[7. .0]
XPOWERSAVE XPW R_SV
AO[8..1]
BO[8..1]
CO[8..1]
OV1_VCKO
CLK
( 15M Hz)
OV1_CLP
EXTCLP
- OE SAD C_OE
OV1_HSNR
FIN-A
OV1_HSNF
FIN-B
OV1_PDEN
PFDINH
OV1 _H
OV1_V
OV1_VCLK
MCK_REF DCLK
V0_HSYNC DO_RA[9.. 2 ]
V0_VSYNC DO_GA[9.. 2 ]
V0_CSYNC DO_BA[9..2]
LCLK
DO_HSYNC
V0_PDEN
DO_VSYNC
DO_HDISP
V0_HSYNR
V0_CLP
V0_HSYNC2
V0_VDCLK_I
V0_RA[7..0]
V0_RB[7..0] BINT
CVIC
V0_GA[7.. 0 ]
V0_GB[7..0]
V0_BA[7..0]
IC25
V0_BB[7..0]
8
V1_GA[7.. 0 ]
8
V1_BA[7..0]
BCLK
8
V1_RA[7..0]
XBCS
V1_VDCLK_O BWAIT
V1_CLP XRESET
PLL_S
V1_HSYNR
V1_HSYNF BD,BA
V1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
SDRAM
512Kx128bitx4 BANK
IC319-322
HY57V653220BTC-7 4 PCS.