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CLKIN
V
VCC5
CC,
ADS, BE3:0, A31:2,
D31:0, LOCK, WAIT,
BLAST,W/R, D/C, DEN,
DT/R, HOLDA,
BLAST, FAIL, SUP,BREQ,
CT3:0, BSTALL, DP3:0,
PCHK
ONCE mode is entered within 1 CLKIN
period after ONCE becomes low while
RESET is low.
RESET
ONCE
NOTES:
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising
edge of RESET.
2. The ONCE input may be removed after the processor enters ONCE mode.
CLKIN may neither float nor remain idle.
It must continue to run.
CLKIN and V
Stable and RESET low and ONCE low to
CC
RESET high, minimum 10,000 CLKIN Periods.
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