Intel 80960HA Datasheet page 18

80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
Name
HOLD
HOLDA
BOFF
BREQ
BSTALL
CT3:0
XINT7:0
NMI
18
Type
HOLD REQUEST signals that an external agent requests access to the
processor's address, data, and control buses. When HOLD is asserted, the
processor:
I
Completes the current bus request.
S(L)
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
O HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
H(1)
the HOLDA state while the RESET pin is asserted.
B(0)
R(Q) HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
I
next clock cycle and the current access is aborted.
S(L)
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See Figure 16 on page 48
O
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
H(Q)
processor stall status. BREQ may be used with BSTALL to indicate to an external
B(Q)
bus arbiter the processor's bus ownership requirements.
R(0)
O
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
H(Q)
regain bus ownership to continue processing (i.e., it may no longer execute
B(Q)
strictly out of on-chip cache memory).
R(0)
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
Cycle Type
Program-initiated access using 8-bit bus
O
Program-initiated access using 16-bit bus
H(Z)
Program-initiated access using 32-bit bus
B(Z)
Event-initiated access using 8-bit bus
R(Z)
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
may be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs may be programmed to be level (low or high) or edge (rising or falling)
I
sensitive.
A(E)
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
A(L)
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least significant bits
of the vectored source are set to "010" internally.
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
A(E)
Description
for BOFF timing requirements.
ADSCT3:0
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
Datasheet