Brefclk - Xilinx RocketIO User Manual

Product Not Recommended for New Designs
Clocking

BREFCLK

At speeds of 2.5 Gb/s or greater, REFCLK configuration introduces more than the
maximum allowable jitter to the RocketIO transceiver. For these higher speeds, BREFCLK
configuration is required. The BREFCLK configuration uses dedicated routing resources
that reduce jitter.
BREFCLK must enter the FPGA through dedicated clock I/O. BREFCLK can connect to the
BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of
USRCLKs. If all the transceivers on a Virtex-II Pro FPGA are to be used, two BREFCLKs
must be created, one for the top of the chip and one for the bottom. These dedicated clocks
use the same clock inputs for all packages:
An attribute (REF_CLK_V_SEL) and a port (REFCLKSEL) determine which reference clock
is used for the MGT PMA block.
selected through use of REFCLKSEL and REF_CLK_V_SEL.
Table 2-3
used for BREFCLK operations.
Table 2-3: BREFCLK Pin Numbers
FG256
FG456
FG676
RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
BREFCLK
Top
BREFCLK2
refclk
refclk2
REFCLKSEL
brefclk
brefclk2
Figure 2-1: REFCLK/BREFCLK Selection Logic
shows the BREFCLK pin numbers for all packages. Note that these pads must be
Package
BREFCLK
Pin Number
A8/B8
C11/D11
B13/C13
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P GCLK4S
N GCLK5P
Bottom
P GCLK2S
N GCLK3P
Figure 2-1 shows how REFCLK and BREFCLK are
REF_CLK_V_SEL
0
1.5V
1
0
to PCS and PMA
1
0
2.5V
1
Top
BREFCLK2
Pin Number
B9/A9
D12/C12
C14/B14
P GCLK6P
BREFCLK
N GCLK7S
P GCLK0P
BREFCLK2
N GCLK1S
refclk_out
ug024_35_091802
Bottom
BREFCLK BREFCLK2
Pin Number Pin Number
R8/T8 T9/R9
W11/Y11 Y12/W12
AD13/AE13 AE14/AD14
R
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