Example 1B: Two-Byte Clock Without Dcm; Example 2: Four-Byte Clock - Xilinx RocketIO User Manual

Clocking

Example 1b: Two-Byte Clock without DCM

If TXDATA and RXDATA are not clocked off the FPGA using the respective USRCLK2s, then the
DCM may be removed from the two-byte clocking scheme, as shown in

Example 2: Four-Byte Clock

If a 4-byte or 1-byte data path is chosen, the ratio between USRCLK and USRCLK2 changes. The
time it take for the SERDES to serialize the parallel data requires the change in ratios.
The DCM example
REFCLK is 156 MHz and USRCLK2_M runs at only 78 MHz, including the clocking for any
interface logic. Both USRCLK and USRCLK2 are aligned on the falling edge, since USRCLK_M
is 180° out of phase when using local inverters with the transceiver.
Clocks for 4-Byte Data Path
VHDL Template
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
.I ( clk_i ),
.O ( USRCLK_M )
);
IBUFG buf2(
.I ( REFCLKIN ),
.O ( REFCLKINBUF )
);
endmodule
Note: Implementation tools automatically
instantiate the BUFG. There is no need to
explicitly instantiate in HDL code.
Figure 2-3: Two-Byte Clock without DCM
(Figure 2-4) is detailed for a 4-byte data path. If 3.125 Gb/s is required,
Note:
These local MGT clock input inverters, shown and noted in
in the FOUR_BYTE_CLK templates.
REFCLK
REFCLK_P
TXUSRCLK
REFCLK_N
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
Figure 2-4: Four-Byte Clock
-- Module: FOUR_BYTE_CLK
-- Description: VHDL submodule
www.xilinx.com
1-800-255-7778
MGT for 2-Byte Data Path (no DCM)
0
IBUFGDS BUFG
REFCLK_P
REFCLK_N
MGT + DCM for 4-Byte Data Path
CLKDV_DIVIDE = 2
IBUFGDS
DCM
CLKIN CLKDV
CLKFB
RST
Figure 2-3:
GT_std_2
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
ug024_02b_062404
Figure 2-4, are not included
GT_std_4
0 REFCLKSEL
BUFG
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLK0
MGT clock input invert-
BUFG
ers (acceptable skew)
UG024_03_112202
R
47