Chipset; System Architecture - SOYO SY-P4IS2 User Manual

Motherboard Description

1-6 CHIPSET

The Intel® 845 chipset Memory Controller Hub (MCH) is designed
for use with the Intel® Pentium 4 processor and Northwood
processor in the 478-pin package. The Intel ® 845 chipset MCH role
in a system is to manage the flow of information between its four
interfaces: the System Bus, the memory interface, the AGP port, and
the Hub Interface. The MCH arbitrates between the four interfaces,
when each initiates an operation. While doing so, the MCH must
support data coherency via snooping and must perform address
translation for access to AGP Aperture memory. To increase system
performance, the MCH incorporates several queues, and a write
cache.
The Intel® 845 chipset Memory Controller Hub (MCH) may contain
design defects or errors known as errata which may cause the
product to deviate from published specifications.

1-6.1 System Architecture

The Intel® 845 chipset Memory Controller Hub (MCH) component
provides the processor interface, DRAM interface, AGP interface,
and Hub Interface in an Intel® 845 chipset desktop platform. The
processor interface supports the Intel® Pentium 4 processor subset
of the Extended Mode of the Scalable Bus Protocol. Intel® 845
chipset is optimized for the Intel® Pentium 4 processor and
Northwood processor. It supports a single channel of PC133
SDRAM. The MCH contains advanced power management logic.
The Intel® 845 chipset platform supports the second generation I/O
Controller Hub (Intel ICH2) to provide the features required by a
desktop platform.
The Intel® 845 chipset MCH is in a 593-pin FC-BGA package and
contains the following functionality:
l
Supports single Intel® Pentium 4 processor/Northwood
processor configurations at 400MHz
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SY-P4IS2