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Motherboard Description
system bus target speed is 400MHz. The MCH does not require any
relationship between the HCLKIN host clock and the 66MHz clock
generated for AGP and Hub Interface; they are totally asynchronous
from each other. The AGP and Hub Interface runs at a constant
66MHz base frequency. The Hub Interface runs at 4x. AGP transfers
may be 2x, or 4x.
The following table indicates the frequency ratios between the
various interfaces that the MCH supports:
Interface
Memory
AGP
Hub interface
1-6.7 System Interrupts
The Intel® 845 chipset MCH supports both 8259 and Intel® Pentium 4
processor interrupt delivery mechanisms. The serial APIC interrupt
mechanism is not supported.
8259 support consists of flushing inbound Hub Interface write buffers
when an Interrupt Acknowledge cycle is forwarded from the system bus to
the Hub Interface.
The Inter® 845 chipset MCH supports the Inter® Pentium 4 processor
interrupt delivery mechanism. IOxAPIC and PCI MSI interrupts are
generated as Memory Writes. The MCH decodes upstream Memory
Writes to the range 0FEE0_0000h – 0FEEF_FFFFh from AGP and the
Hub Interface as message based interrupts. The MCH forwards the
Memory Writes, along with the associated write data, or the system bus as
an Interrupt Message transaction. Note that since this address does not
decode as part of main memory, the write cycle and the write data does not
get forwarded to DRAM via the write buffer. The Inter® 845 chipset MCH
provides the response and TRDY# for all Interrupt Message cycles
Speed
SDR 133 MHz
66 MHz
66 MHz
11
SY-P4IS2
Processor BCLK
(100 MHz)
3:4 synchronous
Asynchronous
Asynchronous
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