Intel S2600CO series User Manual page 140

Appendix C: Integrated BMC Sensor Tables
Full Sensor Name Sensor
(Sensor name in SDR) #
Processor 1 Thermal Margin
74h
(P1 Therm Margin)
Processor 2 Thermal Margin
75h
(P2 Therm Margin)
Processor 1 Thermal
Control %
78h
(P1 Therm Ctrl %)
Processor 2 Thermal
Control %
79h
(P2 Therm Ctrl %)
Processor 1 ERR2 Timeout
7Ch
(P1 ERR2)
Processor 2 ERR2 Timeout
7Dh
(P2 ERR2)
Catastrophic Error
80h
(CATERR)
Processor0 MSID Mismatch
81h
(P0 MSID Mismatch)
Processor Population Fault
82h
(CPU Missing)
Processor1 MSID Mismatch
87h
(P1 MSID Mismatch)
Processor 1 VRD
Temperature
90h
(P1 VRD Hot)
128
Platform Sensor Type Event/
Applicability Reading
Type
Temperature Threshold
All
01h 01h
Temperature Threshold
All
01h 01h
Temperature Threshold
All
01h 01h
Temperature Threshold
All
01h 01h
Digital
Processor
Discrete
All
07h
03h
Digital
Processor
Discrete
All
07h
03h
Digital
Processor
Discrete
All
07h
03h
Digital
Processor
Discrete
All
07h
03h
Digital
Processor
Discrete
All
07h
03h
Digital
Processor
Discrete
All
07h
03h
Digital
Temperature
Discrete
All
01h
05h
Intel order number G42278-004
Event Offset Triggers Contrib. To
System Status
- -
- -
nc =
Degraded
[u] [c,nc]
c = Non-fatal
nc =
Degraded
[u] [c,nc]
c = Non-fatal
01 – State Asserted fatal
01 – State Asserted fatal
01 – State Asserted fatal
01 – State Asserted fatal
01 – State Asserted Fatal
01 – State Asserted fatal
01 - Limit exceeded Non-fatal
Intel® Server Board S2600CO Family TPS
Assert/ Readable Event Rearm
De- Value/ Data
assert Offsets
- Analog R, T
- Analog R, T
As
and Analog Trig Offset
De
As
and Analog Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
As
and – Trig Offset
De
Stand-
by
A –
A –
A –
A –
A –
A –
M –
M –
M –
M –
M –
Revision 1.4