Sdram Cas Latency; Sdram Ras Precharge Time; Dram Integrity Mode - Intel MS-6112 User Manual

SDRAM CAS Latency

This option determines the CAS latency time parameter of SDRAM.
The settings are 2 clks or 3 clks.

SDRAM RAS Precharge Time

This option defines the RAS# precharge requirements for the
SDRAM memory type in 66MHz clocks.

DRAM Integrity Mode

During ECC, this will enable the DRAM ECC mechanism that allows
detection of single-bit and multiple-bit errors and recovery of single-bit
errors. During EC, the ECC logic will calculate 8-bit pattern written along
with 64-bit data into the main memory. During Read operation, 8-bit ECC
code is read along with 64-bit data and error checking is performed. No
correction of data will take place in this operation mode. During Disabled,
this will disable the ECC mechanism.
Note: If you choose ECC or EC modes, you must use a DIMM with ECC
byte.
VGA Frame Buffer USWC
The Pentium
Write-Combining (USWC) memory type. The processor provides a write-
combining with buffering strategy for write operation. This is useful for
frame buffering. Writing to USWC memory can be buffered and combined in
the processors write-combining buffer (WCB). The WCBs are viewed as a
special purpose outgoing write buffers, rather than a cache. The WCBs are
written into memory to allocate a different address, or after executing a
serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
A000 and B000 segment as USWC memory type.
®
II processor supports the Uncacheable Speculatable
3-12
®