Gpctr1_Up_Down Signal; Figure 4-37. Gpctr Timing Summary - National Instruments AT-MIO/AI E Series User Manual

SOURCE
GATE
OUT
National Instruments Corporation

GPCTR1_UP_DOWN Signal

This signal can be externally input on the DIO7 pin and is not available
as an output on the I/O connector. General-purpose counter 1 counts
down when this pin is at a logic low and counts up at a logic high. This
input can be disabled so that software can control the up-down
functionality and leave the DIO7 pin free for general use. Figure 4-37
shows the timing requirements for the GATE and SOURCE input
signals and the timing specifications for the OUT output signals of your
AT E Series board.
V
IH
V
IL
t
gsu
V
IH
V
IL
V
OH
V
OL
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
t
sc
t
gw
t
out
t
sc
t
sp
t
gsu
t
gh
t
gw
t
out

Figure 4-37. GPCTR Timing Summary

4-51
Chapter 4 Signal Connections
t t
sp sp
t
gh
50 ns minimum
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
AT-MIO/AI E Series User Manual