Chapter 2. Architecture And Technical Overview - IBM pSeries 610 model 6C1 Technical Overview And Introduction

Architecture and technical
Chapter 2.
overview
The following sections provide more detailed information about the architecture of the Models
6C1 and 6E1. Figure 2-1 shows the high level system block diagram of both models.
System Planar
3rd serial
port
Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram
© Copyright IBM Corp. 2001, 2002
Processor Card
Memory
512 MB - 8 GB
POWER3-II
333 MHz,
375 MHz, or
450 MHz
Memory
Address
6xx Address Bus
Addr/Cntl
Memory Data Bus
Integrated Service
Processor
ISA Bridge
IDE 10/100 10/100
Super
CD-
Ethernet Ethernet
I/O
ROM
4 MB L2
w/ 333 MHz
166.5 MHz
4 MB L2
w/ 333 MHz
w/ 375 MHz
250 MHz
w/ 375 MHz
225 MHz
w/ 450 MHz
8 MB L2
w/ 450 MHz
16 Bytes @ 95.14 MHz w/ 333 MHz
6xx Data Bus
16 Bytes @ 93.75 MHz w/ 375 MHz
16 Bytes @ 90.00 MHz w/ 450 MHz
16 Bytes @ 95.14 MHz w/ 333 MHz
16 Bytes @ 93.75 MHz w/ 375 MHz
16 Bytes @ 90.00 MHz w/ 450 MHz
SCSI Controller
Internal
External
Ultra3-SCSI Ultra3-SCSI
2
4 MB L2
Processor Card
w/ 333 MHz
166.5 MHz
4 MB L2
w/ 333 MHz
w/ 375 MHz
POW ER3-II
250 MHz
333 MHz,
w/ 375 MHz
375 MHz, or
225 MHz
450 MHz
w/ 450 MHz
8 MB L2
w/ 450 MHz
Data
6xx-MX Bus
66 MHz
PCI Bridge
PCI Bridge
2 PCI Slots
1 PCI Slots
64-bit
64 bit
50 MHz
33 MHz
3.3v
5v
2 PCI Slots
32 bit
33 MHz
5v
9