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24309E—March 2002
Table 10. SYSCLK and SYSCLK# AC Characteristics
Symbol
Parameter Description
Clock Frequency
Duty Cycle
t
Period
1
t
High Time
2
t
Low Time
3
t
Fall Time
4
t
Rise Time
5
Period Stability
Notes:
1. Circuitry driving the AMD Athlon™ system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the
PLL to track the jitter. The –20dB attenuation point, as measured into a 10
2. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
Figure 10. SYSCLK Waveform
Chapter 7
Preliminary Information
Table 10 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of the AMD Athlon XP processor model 6.
Figure 10 shows a sample waveform of the SYSCLK signal.
V
V
Threshold-AC
CROSS
t
5
Electrical Data
AMD Athlon™ XP Processor Model 6 Data Sheet
Minimum
Maximum
50
133
30%
70%
7.5
1.05
1.05
2
2
300
-
-
or 20
pF load must be less than 500 kHz.
t
2
t
4
t
1
Units
Notes
MHz
ns
1, 2
ns
ns
ns
ns
ps
t
3
33
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