Table of Contents
Advertisement
AMD Athlon™ XP Processor Model 10 Data Sheet
FID[3:0] Pins
74
Preliminary Information
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 25 describes the encodings of the clock multipliers on
FID[3:0].
Table 25. FID[3:0] Clock Multiplier Encodings
2
FID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656.
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (serial initialization packet) that is sent to
the processor. The FID[3:0] signals are valid after PWROK is
asserted. The FID[3:0]signals must not be sampled until they
become valid. See the AMD Athlon™ and AMD Duron™ System
Bus Specification, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5-V
tolerant. To prevent damage to the processor, do not pull these
Pin Descriptions
Processor Clock to SYSCLK Frequency Ratio
11
11.5
12
≥ 12.5
1
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
26237C—May 2003
Chapter 11
Advertisement
Table of Contents
