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AMD Athlon™ XP Processor Model 10 Data Sheet
7.2
Advanced 400 FSB AMD Athlon™ XP Processor Model 10
SYSCLK and SYSCLK# AC Characteristics
Table 6.
Advanced 400 FSB SYSCLK and SYSCLK# AC Characteristics
Symbol
Parameter Description
Clock Frequency
Duty Cycle
t
Period
1
t
High Time
2
t
Low Time
3
t
Fall Time
4
t
Rise Time
5
Period Stability
Notes:
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
Figure 9. SYSCLK Waveform
26
Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications
Preliminary Information
Table 6 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of this processor.
Figure 9 shows a sample waveform of the SYSCLK signal.
V
V
Threshold-AC
CROSS
t
5
Minimum
Maximum
50
200
30%
70%
5
1.0
1.0
1.5
1.5
± 300
-
-
or 30
pF load must be less than 500 kHz.
t
2
t
4
t
1
26237C—May 2003
Units
Notes
MHz
1
ns
2, 3
ns
ns
ns
ns
ps
t
3
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