Initialization Role Of Cke; Conditional Self-Refresh; Dynamic Power-Down Operation; Dram I/O Power Management - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

4.3.2.1

Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2

Conditional Self-Refresh

Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on the graphics/display state (relevant only when processor graphics is being used), as
well as memory traffic patterns generated by other connected I/O devices. The target
behavior is to enter self-refresh as long as there are no memory requests to service.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor core flushes pending cycles and then enters all SDRAM ranks into self-
refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh.
4.3.2.3

Dynamic Power-down Operation

Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor core controller can be configured to put the devices in active power-
down (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion
with all pages closed). Precharge power-down provides greater power savings but has
a bigger performance impact, since all pages will first be closed before putting the
devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
4.3.2.4

DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4

PCIe* Power Management

• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
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Power Management
Datasheet, Volume 1