Interface State Combinations; Processor Core Power Management; Enhanced Intel ® Speedstep ® Technology; G, S And C State Combinations - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

Power Management
4.1.7

Interface State Combinations

Table 4-7.

G, S and C State Combinations

Global (G)
State
G0
G0
G0
G0
G1
G1
G2
G3
4.2

Processor Core Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processor's
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
4.2.1 Enhanced Intel
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, V
in steps to an optimized voltage. This voltage is signaled by the SVID bus to the
voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on SVID bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
Datasheet, Volume 1
Processor
Sleep
Package
(S) State
(C) State
S0 C0
S0 C1/C1E
S0 C3
S0 C6
S3 Power off
S4 Power off
S5 Power off
NA Power off
®
SpeedStep
Processor
System Clocks
State
Full On On
Auto-Halt On
Deep Sleep On
Deep Power-
On
down
Off, except RTC
Off, except RTC
Off, except RTC
Power off
®
Technology
Description
Full On
Auto-Halt
Deep Sleep
Deep Power-down
Suspend to RAM
Suspend to Disk
Soft Off
Hard off
is ramped up
CC
45