Pci Express* Configuration Mechanism; Pci Express* Port; Pci Express* Related Register Structures In The Processor - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

2.2.2

PCI Express* Configuration Mechanism

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-4.

PCI Express* Related Register Structures in the Processor

PCI
Express
Device
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(that consists of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3

PCI Express* Port

The PCI Express interface on the processor is a single, 16-lane (x16) port that can also
be configured at narrower widths. The PCI Express port is being designed to be
compliant with the PCI Express Base Specification, Revision 2.0.
26
representing
PEG0
Express ports
(Device 1 and
PCI-PCI
Bridge PCI
Compatible
root PCI Host Bridge
Device
(Device 0)
Device 6)
DMI
Interfaces
Datasheet, Volume 1