Capid0_A-Capabilities A Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.5.33 CAPID0_A—Capabilities A Register
This register control of bits in this register are only required for customer visible SKU
differentiation.
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default:
Bit
31
30
29
28
27
26
25
24
23
22
21
20:19
18
17
16
15
14
13
12
11
10
9:8
80
0/0/0/PCI
E4–E7h
00000000h
RO-FW, RO-KFW
32 bits
000000h
Reset RST/
Attr
Value PWR
RO-KFW 0b
RO-KFW 0b
RO-KFW 0b
RO-KFW 0b
RO-FW 0b
RO-FW 0b
RO-FW 0b
RO-FW 0b
RO-KFW 0b Uncore
RO-FW 0b
RO-FW 0b
RO-FW 00b
RO-FW 0b
RO-FW 0b
RO-FW 0b
RO-KFW 0b
RO-FW 0b Uncore
RO-FW 0b
RO-FW 0b
RO-KFW 0b
RO-FW 0b
RO-FW 00b
Processor Configuration Registers
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VTd Disable (VTDD)
0 = Enable VTd
1 = Disable VTd
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2 DIMMS per Channel Disable (DDPCD)
Allows Dual Channel operation but only supports 1 DIMM per
channel.
0 = 2 DIMMs per channel enabled
1 = 2 DIMMs per channel disabled. This setting hardwires bits
2 and 3 of the rank population field for each channel to
zero. (MCHBAR offset 260h, bits 22–23 for channel 0 and
MCHBAR offset 660h, bits 22–23 for channel 1)
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet, Volume 2