Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 262

B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
23
22
21:16
15:13
12:8
262
0/0/0/VC0PREMAP
8–Fh
00C9008020660262h
RO
64 bits
000h
Reset RST/
Attr
Value PWR
RO 0b Uncore
RO 1b Uncore
RO 100110b Uncore
RO 0h
RO 00010b Uncore
Processor Configuration Registers
Description
Isochrony (ISOCH)
0 = Remapping hardware unit has no critical isochronous
requesters in its scope.
1 = Remapping hardware unit has one or more critical
isochronous requesters in its scope. To guarantee isochronous
performance, software must ensure invalidation operations do
not impact active DMA streams from such requesters. This
implies, when DMA is active, software performs page-
selective invalidations (and not coarser invalidations).
Zero Length Read (ZLR)
0 = Remapping hardware unit blocks (and treats as fault) zero
length DMA read requests to write-only pages.
1 = Remapping hardware unit supports zero length DMA read
requests to write-only pages.
DMA remapping hardware implementations are recommended to
report ZLR field as set.
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability
supported by remapping hardware. The Maximum Guest Address
Width (MGAW) is computed as (N+1), where N is the value
reported in this field. For example, a hardware implementation
supporting 48-bit MGAW reports a value of 47h (101111b) in this
field.
If the value in this field is X, untranslated and translated DMA
requests to addresses above 2^(x+1)–1 are always blocked by
hardware. Translations requests to address above 2^(x+1)–1 from
allowed devices return a null Translation Completion Data Entry
with R=W=0.
Guest addressability for a given DMA request is limited to the
minimum of the value reported through this field and the adjusted
guest address width of the corresponding page-table structure.
(Adjusted guest address widths supported by hardware are
reported through the SAGAW field).
Implementations are recommended to support MGAW at least
equal to the physical addressability (host address width) of the
platform.
Reserved
Supported Adjusted Guest Address Widths (SAGAW)
This 5-bit field indicates the supported adjusted guest address
widths (which in turn represents the levels of page-table walks for
the 4 KB base page size) supported by the hardware
implementation.
A value of 1 in any of these bits indicates the corresponding
adjusted guest address width is supported. The adjusted guest
address widths corresponding to various bit positions within this
field are:
0h = 30-bit AGAW (2-level page table)
1h = 39-bit AGAW (3-level page table)
2h = 48-bit AGAW (4-level page table)
3h = 57-bit AGAW (5-level page table)
4h = 64-bit AGAW (6-level page table)
Software must ensure that the adjusted guest address width used
to setup the page tables is one of the supported guest address
widths reported in this field.
Datasheet, Volume 2