Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 16

The Address Map includes a number of programmable ranges:
• Device 0
— PXPEPBAR – PxP egress port registers. (4 KB window)
— MCHBAR – Memory mapped range for internal MCH registers. (32 KB window)
— DMIBAR – This window is used to access registers associated with the
processor/PCH Serial Interconnect (DMI) register memory range. (4 KB
window)
— GGC.GMS – Graphics Mode Select. Used to select the amount of main memory
that is pre-allocated to support the internal graphics device in VGA (non-linear)
and Native (linear) modes. (0–512 MB options).
— GGC.GGMS – GTT Graphics Memory Size. Used to select the amount of main
memory that is pre- allocated to support the Internal Graphics Translation Table.
(0–2 MB options).
For each of the following 4 device functions
• Device 1, Function 0
• Device 1, Function 1
• Device 1, Function 2
• Device 6, Function 0
— MBASE/MLIMIT – PCI Express port non-prefetchable memory access window.
— PMBASE/PMLIMIT – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access
window
— IOBASE/IOLIMIT – PCI Express port I/O access window.
• Device 2, Function 0
— IOBAR – I/O access window for internal graphics. Through this window
address/data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be acces sed. Note, this allows accessing the same
registers as GTTMMADR. The IOBAR can be used to issue writes to the
GTTMMADR or the GTT table.
— GMADR – Internal graphics translation window (128 MB, 256 MB, 512 MB
window).
— GTTMMADR – This register requests a 4 MB allocation for combined Graphics
Translation Table Modification Range and Memory Mapped Range. GTTADR will
be at GTTMMADR + 2 MB while the MMIO base address will be the same as
GTTMMADR.
The rules for the above programmable ranges are:
1. For security reasons, the processor will now positively decode (FFE0_0000h to
FFFF_FFFFh) to DMI. This ensures the boot vector and BIOS execute off PCH.
2. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designers' responsibility to limit memory population so that adequate PCI,
PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory
space can be allocated.
3. In the case of overlapping ranges with memory, the memory decode will be given
priority. This is a Intel TXT requirement. It is necessary to get Intel TXT protection
checks, avoiding potential attacks.
4. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
5. Accesses to overlapped ranges may produce indeterminate results.
6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
requests that cross a DW boundary
16
Processor Configuration Registers
Datasheet, Volume 2