Pciexpress Root Port Function - JETWAY 917PDCPR106 User Manual

PCIExpress Root Port Function

Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Transfer Mode
In this item you can select AGP transfer mode Auto/4X/1X the Default setting is Auto.
3-6-1 PCIExpress Root Port Function
PCIExpress Port 1
PCIExpress Compliancy Mode
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Phoenix – AwardBIOS CMOS Setup Utility
PCIExpress Root Port Function
Auto
v1.0a
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
34
Item Help
F1:General Help