Advanced Chipset Features; Dram Timing Settings - JETWAY 830CF User Manual

M/b for socket-a athlon/duron processor

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User manual (57 pages)

Table Of Contents

Table of Contents

DRAM Timing Settings

AGP Function Settings

PCI GRANT Parking on

Memory Parity Check

System BIOS Cacheable

Video RAM Cacheable

Memory Hole at 15M-16M

System Share Memory Size

↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit

F5:Previous Values

DRAM Timing Settings

Please refer to section 3-6-1

AGP Function Settings

This option determines the effective size of the graphics aperture used in the particular PAC

configuration. The AGP aperture is memory-mapped, while graphics data structure can reside

in a graphics aperture. The aperture range should be programmed as not cacheable in the

processor cache, accesses with the aperture range are forwarded to the main memory, then

PAC will translate the original issued address via a translation table that is maintained on the

main memory. The option allows the selection of an aperture size of 32MB, 64MB.

Please refer to section 3-6-2

PCI GRANT Parking On

The settings are: PMR, PCI Master.

Memory Parity Check

This function provides parity check of memory.

The choice is either Disabled or Enabled.

System BIOS Cacheable

Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in

better system performance. However, if any program writes to this memory area, a system

error may result. The settings are: Enabled and Disabled.

Video RAM Cacheable

Select Enabled allows caching of the video BIOS, resulting in better system performance.

However, if any program writes to this memory area, a system error may result. The settings

are: Enabled and Disabled.

Memory Hole at 15M-16M

You can reserve this area of system memory for ISA adapter ROM. When this area is

reserved, it cannot be cached. The user information of peripherals that need to use this area of