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Texas Instruments DS90UH927Q Manual

5mhz - 85mhz 24-bit color fpd-link iii serializer with hdcp

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5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP
General Description
The DS90UH927Q serializer, in conjunction with a
DS90UH928Q or DS90UH926Q deserializer, provides a so-
lution for secure distribution of content-protected digital video
within automotive entertainment systems. This chipset trans-
lates a FPD-Link video interface into a single-pair high-speed
serialized interface. The digital video data is protected using
the industry standard High-Bandwidth Digital Content Protec-
tion (HDCP) copy protection scheme. The FPD-Link III serial
bus scheme supports full duplex, high speed forward channel
data transmission and low-speed back channel communica-
tion over a single differential link. Consolidation of audio,
video, and control data over a single differential pair reduces
the interconnect size and weight, while also eliminating skew
issues and simplifying system design.
The DS90UH927Q serializer embeds the clock, content pro-
tects the data payload, and level shifts the signals to high-
speed differential signaling. Up to 24 RGB data bits are
serialized along with three video control signals, and up to four
I2S data inputs.
The FPD-Link data interface allows for easy interfacing with
data sources while also minimizing EMI and bus width. EMI
on the high-speed FPD-Link III bus is minimized using low
voltage differential signaling, data scrambling and random-
ization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer
and deserializer. HDCP keys are stored in on-chip memory.
Applications Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
Features
Integrated HDCP cipher engine with on-chip key storage
Bidirectional control channel interface with I2C compatible
serial control bus
Low EMI FPD-Link video input
Supports high definition (720p) digital video format
5MHz – 85MHz PCLK supported
RGB888 + VS, HS, DE and I2S audio supported
Up to 4 I2S Digital Audio inputs for surround sound
applications
4 Bidirectional GPIO channels with 2 dedicated pins
Single 3.3V supply with 1.8V or 3.3V compatible LVCMOS
I/O interface
AC-coupled STP Interconnect up to 10 meters
DC-balanced & scrambled Data with Embedded Clock
Supports HDCP repeater application
Internal pattern generation
Low power modes minimize power dissipation
Automotive grade product: AEC-Q100 Grade 2 qualified
>8kV HBM and ISO 10605 ESD rating
Backward compatible modes
Applications
Automotive Display for Navigation
Rear Seat Entertainment Systems
301930 SNLS433A
Copyright © 1999-2012, Texas Instruments Incorporated
DS90UH927Q
30193027

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Summary of Contents for Texas Instruments DS90UH927Q

  • Page 1 ● AC-coupled STP Interconnect up to 10 meters The DS90UH927Q serializer embeds the clock, content pro- ● DC-balanced & scrambled Data with Embedded Clock tects the data payload, and level shifts the signals to high- ●...
  • Page 2: Table Of Contents

    Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs I2S_CLK w/ pull down Shared with GPIO_REG7 and GPIO_REG8 Table 3 I2S_DA I, LVCMOS Digital Audio Interface I2S Data Inputs I2S_DB w/ pull down Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3 I2S_DC I2S_DD Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 3: Pin Name Pin

    INTB = H, normal INTB = L, Interrupt request Recommended pull-up: 4.7kΩ to V . DO NOT FLOAT. DDIO FPD-Link III Serial Interface DOUT+ I/O, LVDS True Output The output must be AC-coupled with a 0.1µF capacitor. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 4 Requires two 4.7µF decoupling capacitors to GND Other RES[1:0] 15, 13 Reserved Connect to GND. * The V and V ) supply ramp should be faster than 1.5 ms with a monotonic rise. DD33 DDIO Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 5 Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to http://www.ti.com/automotive. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 6 DS90UH927Q Absolute Maximum Ratings (Note If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Parameter DS90UH927Q Unit Supply Voltage – V −0.3 to +4.0 DD33 Supply Voltage – V −0.3 to +4.0...
  • Page 7: Rxin[3:0]

    , PDB = L, TRI-STATE® Output Current −15 DDIO FPD-Link LVDS Receiver Threshold High Voltage +100 Threshold Low Voltage −100 = 1.2V Differential Input Voltage RxCLKIN± Swing RxIN[3:0]± Common Mode Voltage μA Input Current −10 Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 8 DDIO Auto Power Down Idle DDIOS DDIO μA 1.89V = 3.6V DD33 μA = 3.6V PDB = 0V, All other LVCMOS DDIO Supply Current — Power Down inputs = 0V DDIOZ DDIO μA 1.89V Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 9 I2S Set-up Time I2S_WC I2S_D [A,B,C,D] I2S Hold Time I2S_WC I2S_D [A,B,C,D] Other I/O GPIO[3:0], GPIO Pulse Width, Forward PCLK = >2/ GPIO,FC Channel 5MHz to PCLK 85MHz GPIO Pulse Width, Back GPIO[3:0] GPIO,BC µs Channel Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 10 SDA, RPU = 10kΩ, Cb 400pF, Figure 9 SDA Fall Time – READ Set Up Time — READ Figure 9 SU;DAT Hold Up Time — READ Figure 9 HD;DAT Input Filter Input Capacitance SDA or SCL <5 Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 11 Note 11: UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency. Note 12: Output jitter specs are dependent upon the input clock jitter at the SER Note 13: The DS90UH927Q V and V voltages require a specific ramp rate during power up.
  • Page 12 DS90UH927Q AC Timing Diagrams and Test Circuits 30193013 FIGURE 1. FPD-Link DC V Definition 30193062 FIGURE 2. Serializer V DC Output 30193047 FIGURE 3. Output Transition Times Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 13 DS90UH927Q 30193014 FIGURE 4. FPD-Link Input Strobe Position 30193049 FIGURE 5. Serializer Lock Time 30193015 FIGURE 6. Latency Delay Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 14 DS90UH927Q 30193048 FIGURE 7. CML Serializer Output Jitter 30193046 FIGURE 8. Checkerboard Data Pattern 30193036 FIGURE 9. Serial Control Bus Timing Diagram Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 15 DS90UH927Q 30193006 FIGURE 10. I2S Timing Diagram Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 16 Functional Description The DS90UH927Q converts a FPD-Link interface (4 LVDS data channels + 1 LVDS Clock) to a FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating at up to a 2.975Gbps line rate. The serial stream contains an embedded clock, video control signals, RGB video data, and audio data.
  • Page 17: Table

    The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations relative to the video pixel clock period (PCLK). By default, the DS90UH927Q applies a minimum pulse width filter on these signals to help eliminate spurious transitions.
  • Page 18 See AC Electrical Characteristics for more information. REMOTE AUTO POWER DOWN MODE The DS90UH927Q serializer features a Remote Auto Power Down mode. This feature is enabled and disabled through the register bit 0x01[7] (Table 5).
  • Page 19 5) for more information. SERIAL LINK FAULT DETECT The DS90UH927Q can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 5).
  • Page 20 Input, Read: 0x1C[0] I2S AUDIO INTERFACE The DS90UH927Q serializer features six I2S input pins that, when paired with a DS90UH928Q deserializer, supports surround sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1MHz and the smaller of <PCLK/2 or <13MHz.
  • Page 21 I2S_DA and I2S_DB only is desired, this mode must be explicitly set in each serializer and deserializer control register throughout the repeater tree (Table A DS90UH927Q serializer configured in repeater mode may also regenerate I2S audio from its I2S input pins in lieu of Data Island frames. See the HDCP Repeater Connection Diagram (Figure...
  • Page 22 On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the device. The DS90UH927Q uses the Cipher engine to encrypt the data as per HDCP v1.3. The encrypted data is sent through the FPD- Link III interface.
  • Page 23 IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address. REPEAT pin — All HDCP Transmitters and Receivers must be set into Repeater Mode. Interrupt pin – Connect DS90UH928Q INTB_IN pin to DS90UH927Q INTB pin. The signal must be pulled up to V DDIO...
  • Page 24 30193042 FIGURE 19. HDCP Repeater Connection Diagram REPEATER FAN-OUT ELECTRICAL REQUIREMENTS Repeater applications requiring fan-out from one DS90UH928Q deserializer to up to three DS90UH927Q serializers requires spe- cial considerations for routing and termination of the FPD-Link differential traces. Figure 20...
  • Page 25 HDCP encryption of digital audio may be required. System designers should consult the specific HDCP spec- ifications to determine if encryption of digital audio is required by the specific application audiovisual source. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 26 The desired clock source is selected through the deserializer BISTC pin. Step 2: The DS90UH927Q serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream.
  • Page 27 For detailed information, refer to Application Note AN-2198. PATTERN OPTIONS The DS90UH927Q serializer pattern generator is capable of generating 17 default patterns for use in basic testing and debugging of panels. Each can be inverted using register bits...
  • Page 28 Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 5) and the Pattern Generator Indirect Data (PGID reg_0x67 — Table 5). See TI application Note AN-2198. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 29 Serial Control Bus The DS90UH927Q may also be configured by the use of a I2C compatible serial control bus. Multiple devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 23 below) connected to the IDx pin.
  • Page 30 30193039 FIGURE 26. Serial Control Bus — WRITE The I2C Master located at the DS90UH927Q serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, please refer to TI Application Note SNLA131. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 31 DeviceAlias registers will be passed through to the remote deserializer I2C interface. 0: Pass-Through Disabled (default) 1: Pass-Through Enabled Reserved PCLK Switch over to internal OSC in the absence of Auto PCLK 0: Disable auto-switch 1: Enable auto-switch (default) TRFB Reserved Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 32 0: Frequency mode is set by LFMODE pin (default) 1: Frequency mode is set by register bit LFMODE Frequency mode select ≤ ≤ 0: High frequency mode (15MHz RxCLKIN 85MHz) (default) ≤ 1: Low frequency mode (5MHz RxCLKIN < 15 MHz) Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 33 Deserializer. If an I2C transaction is addressed to the Slave Device Alias ID 0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. Reserved Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 34 The GPIO pin will be an output, and the value is received from the remote Deserializer. GPIO0 Local GPIO Direction Direction 0: Output (default) 1: Input GPIO0 GPIO Function Enable Enable 0: Enable normal operation (default) 1: Enable GPIO operation Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 35 The GPIO pin will be an output, and the value is received from the remote Deserializer. GPIO3 Local GPIO Direction Direction 0: Output (default) 1: Input GPIO3 GPIO Function Enable Enable 0: Enable normal operation (default) 1: Enable GPIO operation Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 36 GPIO direction is Output. 0: Output LOW (default) 1: Output HIGH Reserved GPIO_RE Local GPIO Direction 0: Output (default) Direction 1: Input GPO_RE GPIO Function Enable G7 Enable 0: Enable normal operation (default) 1: Enable GPIO operation Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 37 0: Enable I2S Data Island Transport (default) Select 1: Enable I2S Data Forward Channel Frame Transport I2S Channel B Enable Channel B 0: I2S Channel B disabled (default) Enable 1: Enable I2S Channel B Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 38 Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. Timer Disable BCC Watchdog Timer Control 0: Enable BCC Watchdog Timer operation (default) 1: Disable BCC Watchdog Timer operation Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 39 BIST BC BIST Back Channel CRC Error Counter Count Errorr This register stores the back-channel CRC error count during BIST Mode (saturates at 255 errors). Clears when a new BIST is initiated or by 0x04[5] Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 40 Status valid only if set to GPI (input) mode Status 0x1F Frequency 0x00 Frequency Frequency Counter Control Counter Counter Write: Measure number of pixel clock periods in written interval (40ns units) Read: Return number of pixel clock periods counted Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 41 Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. 0: Normal operation (default) 1: Freeze Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 42 Pattern 0: Color sequence from top left is (YCBR) (default) Reverse 1: Color sequence from top left is (RBCY) Pattern Pattern Generator Enable Generator 0: Disable Pattern Generator (default) Enable 1: Enable Pattern Generator Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 43 This 8-bit field sets the indirect address for Indirect accesses to indirectly-mapped registers. It should Address be written prior to reading or writing the Pattern Generator Indirect Data register. See TI App Note AN-2198 Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 44 I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. Reserved Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 45 I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 46 TX_AN4: Value of byte 4 of the Serializer AN Value 0x9D TX_AN5 0x00 TX AN5 TX_AN5: Value of byte 5 of the Serializer AN Value 0x9E TX_AN6 0x00 TX AN6 TX_AN6: Value of byte 6 of the Serializer AN Value Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 47 Indicates the number of attached levels of devices Depth for the Repeater 0xA3 KSV FIFO 0x00 KSV FIFO KSV FIFO Each read of the KSV FIFO returns one byte of the KSV FIFO list composed by the downstream Receiver. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 48 Setting this bit to a 1 will enable the HDCP I2C Master in the HDCP Receiver to operate with Fast mode timing. If set to a 0, the I2C Master will operate with Standard mode timing. This bit is mirrored in the IND_STS register Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 49 Enable AVMUTE This bit may only be set if the MUTE HDCP_EESS bit is also set. 0: Resume normal operation (default) 1: Initiate AVMUTE operation. The transmitter will ignore encryption status controls while in this state. Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 50 Enables HDCP authentication. If HDCP is already enabled, setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A register read will return the current HDCP enabled status Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 51 HDCP Authenticated Indicates the HDCP authentication has completed successfully. The controller may now send video data requiring content protection. This bit will be cleared if authentication is lost or if the controller restarts authentication Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 52 IS AUTH Interrupt on Authentication Failure FAIL Authentication failure or loss of authentication has occurred IS AUTH Interrupt on Authentication Pass PASS Authentication has completed successfully Global Interrupt Set if any enabled interrupt is indicated Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 53 Second byte of ID code, ‘U’ 0xF2 0x48 Third byte of ID code. ‘H' 0xF3 0x39 Forth byte of ID code: ‘9’ 0xF4 0x32 Fifth byte of ID code: “2” 0xF5 0x37 Sixth byte of ID code: “7” Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 54 Figure 27 shows a typical application of the DS90UH927Q serializer for an 85 MHz 24-bit Color Display Application. The 5 LVDS input pairs require external 100Ω terminations. The CML outputs must have an external 0.1µF AC coupling capacitor on the high speed serial lines.
  • Page 55 In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. For DS90UH927Q, only one common ground plane is required to connect all device related ground pins.
  • Page 56 DS90UH927Q Revision • October 26, 2012 — Initial Release Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 57 DS90UH927Q Physical Dimensions inches (millimeters) unless otherwise noted 40–pin LLP Package (6.0 mm X 6.0 mm X 0.8 mm, 0.5 mm pitch) TI Package Number SQA40A Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 58 Notes Copyright © 1999-2012, Texas Instruments Incorporated...
  • Page 59 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.