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Application Note
DP83867 Troubleshooting Guide
Evan Mayhew, Patrick O'Farrell, Hillman Lin
1
Introduction.............................................................................................................................................................................2
Application...........................................................................................................................................3
2.2 Schematic and Layout Checklist........................................................................................................................................
2.3 Component Checklist.........................................................................................................................................................
Checks........................................................................................................................................................5
2.5 Link Quality Check...........................................................................................................................................................
2.6 Built-in Self Test With Various Loopback Modes..............................................................................................................
Interface................................................................................................................................................14
3 Application Specific Debugs...............................................................................................................................................
3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps...........................................................................................
Debug...........................................................................................................................................................21
Debug......................................................................................................................................................................22
3.8 Tools and References......................................................................................................................................................
4 Conclusion............................................................................................................................................................................
5 References............................................................................................................................................................................
6 Revision History...................................................................................................................................................................
Trademarks
All trademarks are the property of their respective owners.
SNLA246C - OCTOBER 2015 - REVISED APRIL 2024
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Table of Contents
Check.................................................................................................3
Cables....................................................................................................................18
Channels..........................................................................................................19
Mode...................................................................................................................19
communication..........................................................................................................19
Copyright © 2024 Texas Instruments Incorporated
Table of Contents
DP83867 Troubleshooting Guide
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Summary of Contents for Texas Instruments DP83867
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Page 1: Table Of Contents
3.8 Tools and References..............................4 Conclusion.................................... 5 References.................................... 6 Revision History................................... Trademarks All trademarks are the property of their respective owners. SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated... -
Page 2: Introduction
Status Crystal or Oscillator LEDs Figure 1-1. DP83867 Block Diagram The DP83867 can connect to an Ethernet MAC and to a media. The connection to the media is via a transformer and a connector. Table 1-1. DP83867 Configurations DP83867 Version... -
Page 3: Troubleshooting The Application
The expected register values for PHY operation and link in 1000 Mbps with auto-negotiation enabled are shown Table 2-1. Table 2-1. DP83867 Register Value References Register Address (h) Register Value (h) Comments 0x0000 0x1140 MII loopback;... -
Page 4: Schematic And Layout Checklist
– At or lower than the magnitude specified in data sheet. If specification gives -16dB as typical, finding a component with -16dB, -17dB, … is recommended. DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated... -
Page 5: Peripheral Pin Checks
(Die Attach Pad (Die Attach Pad Figure 2-2. Three Supply Configuration Figure 2-1. Two Supply Configuration The DP83867 supports two configurations for power supplies as shown in Figure 2-1 Figure 2-2. DP83867 can operate with as few as two supplies. When operating in the three-supply configuration, the VDDA1P8 supply SNLA246C –... - Page 6 25ms of the VDDA2P5 supply ramping up. There is no sequencing requirement for other supplies when operating in three supply mode. When powering down the DP83867, the VDDA1P8 supply needs to be brought down before the VDDA2P5 supply. Power up the board and verify the sequence of these supplies with an oscilloscope.
- Page 7 For further confirmation, the strap values can be read from the registers. The values are available in register 0x006E (STRAP_STS1) and register 0x006F (STRAP_STS2). Section 3.8.2 SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
- Page 8 Figure 2-4. Typical MDC/MDIO Read Operation Figure 2-5. Typical MDC/MDIO Write Operation Note Recommend using Logic Analyzer to debug MDIO communication. DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
- Page 9 Figure 2-6. 100 Ohm Terminated Cable for MDI Signal Measurement Oscilloscope Differential Probe 100Q 100Q RJ-45 100Q 100Q Figure 2-7. Connection Diagram for 100M Terminated Cable SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
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Page 10: Link Quality Check
The bursts are nominally 2ms in duration and occur every 16ms. An example link pulse is shown below Figure 2-8. Figure 2-8. DP83867 Link Pulse Observing this pulse confirms the PHY is on and attempting to link. 2.5 Link Quality Check... -
Page 11: Built-In Self Test With Various Loopback Modes
MII loopack, PCS loopback, Digital Loopback, and Analog Loopback could isolate the PHY < -- > PHY communication. Reverse Loopback could isolate the MAC < -- > PHY communication. The following diagrams illustrate the various loopback mode that DP83867 have: PCS Loopback... - Page 12 1. Power and connect the PHY to the MAC and a working link partner. 2. Enable reverse loopback on the link partner (for DP83867 link partner, write 0x16 to 0020). 3. Transmit test packets from the MAC to the PHY.
- Page 13 // Repeat (4) and (5) as desired to verify packet count changing for each counter update Register 0x17[11] indicates whether PRBS was able to successfully receive the same transmitted data through the given data path. SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
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Page 14: Debugging Mac Interface
Verify the frequency of the clock (C2) as 2.5MHz, and the data (C1) being sampled at the rising edge of the clock. DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated... - Page 15 For the PHY set in RX shift mode (0x32) in 10/100Mbps, probe the clock and data signals on the MAC end and compare to the following reference waveforms. SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
- Page 16 For the PHY set in TX shift or align mode, probe the data and clock signals on the PHY end and verify the timing requirements below are met: DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
- Page 17 4. Take a look on the trace length and impedance on the SGMII lines and make sure it follows the DP83867 Layout Checklist. 5. Write software reset 0x001F to 4000 or restarting SGMII auto-negotiation by register 0x0014 bit[7]. SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
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Page 18: Application Specific Debugs
3 Application Specific Debugs 3.1 Improving Link-up Margins for Short Cables If you are encountering an issue with packet loss or CRC errors while using the DP83867, please consider some of these items for debug when using short cables. Short cables at 1m or less in length for your device can experience signal quality issues. One reason could be that the digital signal processing internally can take too long to converge or can converge to suboptimal filter values at shorter lengths which can result to a bad SNR - Signal to Noise Ratio. -
Page 19: Improving Link Margins Across Different Channels
100Mbps full duplex mode in register 0x0000. 3.4 Unstable Link Up Debug in 1Gbps communication If repeating link up and link down between Dp83867 and another Link Partner behavior occur, please follow this session for debug: 1. Write register 0x001F to 4000 (software reset) and see if you are able to link up. -
Page 20: Dp83867Phy And Dp83867Phy Cannot Link Up In 1Gbps
– However, the PRN is not exactly random and if both DP83867 start auto-negotiation at the same time, there is a possibility both DP83867 send out the exact same random seed (PRN) and result in dead lock. Solution: – Write 0x0009 bit[12:11] to 11 on one of the DP83867PHY and write 0x0009 bit[12 :11] to 10 on another DP83867PHY. -
Page 21: Compliance Debug
If all schematic, layout checklist, and compliance test application note do not help, adjusting register 0x00A0, 0x00A1, 0x00A2, 0x00A3 can help with compliance test. Note Default values of 0x00A1 and 0x00A2 registers are trimmed. SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 DP83867 Troubleshooting Guide Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated... -
Page 22: Emc Debug
– Check length matching and impedance matching for MDI lines – No vias around the MDI lines – Follow the layout checklist in Section 2.2 • If customer is struggling on conducted immunity IEC61000 4-6 on DP83867 PHY, please program the following script: – begin 008A 010F... -
Page 23: Tools And References
MSP430 Launchpad, and purchased through TI.com. The GUI supports reading and writing registers as well as running script files. USB-2-MDIO GUI can be used with the DP83867 and the other devices in TI's Ethernet portfolio. The USB-2-MDIO User's Guide and GUI are available for download at:... - Page 24 Above write and read procedure is normally used for registers with address greater than 0x001F. But the procedure can also be used for any address in general. DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
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Page 25: Conclusion
Conclusion 4 Conclusion This application note provides a suggested flow for evaluating a new application and confirming the expected functionality. The step-by-step recommendations will help ease board bring up and initial evaluation of DP83867 designs. 5 References 1. Texas Instruments, How to Pass IEEE Ethernet Compliance Tests, application note. -
Page 26: Revision History
Changed images for USB-2-MDIO GUI and MSP430 LaunchPad in Section 3.8.1 ........23 • Changed format of USB-2-MDIO link....................... • Added example script for USB-2-MDIO......................23 DP83867 Troubleshooting Guide SNLA246C – OCTOBER 2015 – REVISED APRIL 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated... - Page 27 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...