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Chapter 2
Hardware Overview
4 Camera Control Lines
4 External Triggers
External PCLK,
HSYNC, VSYNC
Genlock Circuit
External CSYNC
and SYNC Mux
Video
Video
Mux
Programmable
0,1,2,3
Gain and Offset
Video 0
Video Multiplexer
Programmable Gain and Offset
Analog Bandwidth Control Circuitry
10-Bit ADC
NI PCI-1410 User Manual
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The block diagram in Figure 2-1 illustrates the key functional units of the
NI 1410.
RTSI Bus
Digital
Input/Output
Circuitry
Aspect Ratio Correction
HSYNC, VSYNC
PCLK
Analog
Bandwidth
10-Bit
Control
ADC
Circuitry
Figure 2-1. NI 1410 Block Diagram
The video multiplexer routes one of the four AC-coupled video inputs to
the 10-bit ADC circuitry. The input impedance is 75 Ω.
The NI 1410 uses programmable gain and offset circuitry to optimize the
input signal range.
You can select either the full bandwidth of 30 MHz or a reduced bandwidth
of 9 MHz. The 9 MHz bandwidth setting is available using a 5th order
Butterworth lowpass filter.
The 10-bit ADC digitizes the conditioned video signal.
2-2
Acquisition and
Region-of-Interest
Control
Digital
Onboard
Filter
Memory and
and
Control Circuitry
LUT
PCI Interface and
Scatter-Gather
DMA Controller
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