Boot Modes; Sys_Boot Switch Settings - Texas Instruments DRA7 Series User Manual

Hardware
3.3

Boot Modes

Multiple boot modes are supported as determined by the 16-bit "system boot" setting present on the
shared specific I/O balls during power-on sequence. For more information, see the device-specific
technical reference manual (TRM). These shared I/O resources can be "redeployed" to support alternate
interfaces after boot-up by changing of the on-die mux mode settings per I/O and configuring CPU board's
on-board bus logic switches. Boot mode selection is accomplished by the setting of DIP switches SW2
and SW3 as shown in
Interface
(Internal System Boot Input)
GPMC_AD0
(sysboot0)
GPMC_AD1
(sysboot1)
GPMC_AD2
(sysboot2)
GPMC_AD3
(sysboot3)
GPMC_AD4
(sysboot4)
GPMC_AD5
(sysboot5)
GPMC_AD6
(sysboot6)
GPMC_AD7
(sysboot7)
GPMC_AD8
(sysboot8)
GPMC_AD9
(sysboot9)
GPMC_AD10
(sysboot10)
GPMC_AD11
(sysboot11)
GPMC_AD12
(sysboot12)
GPMC_AD13
(sysboot13)
GPMC_AD14
(sysboot14)
GPMC_AD15
(sysboot15)
3.3.1 On-Board Boot Routing Control
CPU board has external, on-board multiplexing bus logic switches to enhance the flexibility of the EVM.
Multiplexing options on-board should be selected accordingly to the desired boot mode to enable interface
paths required to access desired boot devices or port. DIP Switch SW5 has 10 individual SPST positions.
Positions 1-5 have been used to control board signal routing for booting. Positions 6-10 have been used to
control other CPU board signaling paths and modes of operation.
SW5 DIP switches connect nets to strong (1k) pull-down resistors to ground when a switch is set to the
"ON" position, corresponding to a "Low" logic level signal. Alternatively, when switch is in the "OFF"
position, a 10k pull-up connects it to 3.3 V rail, corresponding to a "High" logic level signal.
12
DRA7x EVM CPU Board
Table 9.
Table 9. SYS_Boot Switch Settings
CPU Bd Net
GPMC_D00
GPMC_D01
GPMC_D02
GPMC_D03
GPMC_D04
GPMC_D05
GPMC_D06
GPMC_D07
GPMC_D08
GPMC_D09
GPMC_D10
GPMC_D11
GPMC_D12
GPMC_D13
GPMC_D14
GPMC_D15
Copyright © 2016, Texas Instruments Incorporated
DIP Switch Ref Des
Position No Connections
SW2.P1
SW2.P2
SW2.P3
SW2.P4
SW2.P5
SW2.P6
SW2.P7
SW2.P8
SW3.P1
SW3.P2
SW3.P3
SW3.P4
SW3.P5
SW3.P6
SW3.P7
SW3.P8
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Factory Settings
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
SPRUI50 – February 2016
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