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2.6 Boot Mode Selection
The bootmode for the AM263x is selected by either the DIP switch (SW3) or the test automation header. The
test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. The
supported boot modes are as shown in
Boot Mode/Peripheral
QSPI (4S) - Quad Read Mode
UART
QSPI (1S) - Single Read Mode
QSPI (4S) - Quad Read UART
Fallback Mode
QSPI (1S) - Single Read UART
Fallback Mode
DevBoot
Boot Mode
QSPI (4S) - Quad Read Mode
UART
QSPI (1S) - Single Read Mode
QSPI (4S) - Quad Read UART Fallback
Mode
QSPI (1S) - Single Read UART Fallback
Mode
DevBoot
Unsupported Boot Mode
SPRUJ93 – AUGUST 2023
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Supported Boot
Modes.
Table 2-4. Supported Boot Modes
Boot Media/Host
Notes
QSPI Flash
Download and boot SBL from QSPI flash in quad read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails.
External Host
Download and boot SBL from UART. Device is expected to get SBL
from UART. Device supports the XMODEM protocol for download over
UART.
QSPI Flash
Download and boot SBL from QSPI flash in single read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails.
QSPI Flash / External Host Download and boot SBL from QSPI flash in quad read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails. If
Secondary SBL also fails then boot from external host via UART
interface.
QSPI Flash / External Host Download and boot SBL from QSPI flash in single read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails. If
Secondary SBL also fails then boot from external host via UART
interface.
N/A
No SBL. Used for development purposes only.
Figure 2-14. SW3 Switch Positions
Table 2-5. Boot-Mode Selection Table
SPI0_D0_pad
(SOP3)
0
0
0
0
0
1
Copyright © 2023 Texas Instruments Incorporated
SPI0_CLK_pad
(SOP2)
QSPI_D1 (SOP1)
0
0
0
0
0
1
1
0
1
0
0
1
All other combinations not defined above
AM263x Control Card with PMIC and Automotive Ethernet
Hardware
QSPI_D0 (SOP0)
0
1
0
0
1
1
19
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