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Hardware
VIN4B vs RGMII0
VIN4B and RGMII0
Use Bit "P4" in I2C IO Expander (U57) with slave address 0x0100 0010(Write) to control, signal
"SEL_ENET_MUX_S0".
3.4.8
VIN6A Vs McASP1, 2, 3 and 7
Multiplex control logic for VIN6A and McASP1, 2, 3 and 7.
The default interface is VIN6A to the expansion connector and the selection table is shown in
VIN6A vs McASP1,2,3 and 7
VIN6A/McASP1,2,3 and 7
Use Bit "P1" in I2C IO Expander (U119) with slave address 0x0100 0100(Write) to control, signal
"VIN6_SEL_S0".
3.4.9
UART3 Vs SPI[2]
Multiplex control logic for UART3 and SPI[2].
20
DRA7x EVM CPU Board
Table 18. VIN4B and RGMII0 Selection Table
SEL_ENET_MUX_S0
1
0
Figure 13. VIN6A and McASP1, 2, 3 and 7 Multiplexing
Table 19. VIN6A and McASP1, 2, 3 and 7 Selection Table
VIN6_SEL_S0
1
0
Figure 14. UART3 and SPI[2] Multiplexing
Copyright © 2016, Texas Instruments Incorporated
Interface
RGMII0
VIN4B/GPIO's
Interface
VIN6A
McASP1,2,3 and 7
TLV320AIC3106, COM8 Conn,
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Device
Gbit Ethernet PHY
Expansion Connector
Table
19.
Device
Expansion Connector
Exp.Conn.
SPRUI50 – February 2016
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