Table of Contents
Advertisement
BQ77307
SLUSF60 – DECEMBER 2023
higher voltage, since this would forward bias these diodes. During cell attach, the cell input terminals should
generally be floating before they are connected to the appropriate cell. It is expected that transient current will
flow briefly when each cell is attached, but the cell voltages will quickly stabilize to a state without DC current
flowing through the diodes. However, if a large capacitance is included between a cell input pin and another
terminal (such as VSS or another cell input pin), the transient current may become excessive and lead to
device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin to the values
recommended in the specifications.
8.2.5 Startup Timing
At the initial power-up of the BQ77307 device from a SHUTDOWN state, the device progresses through a
sequence of events before entering NORMAL mode operation. These events are described below for two
example configurations, with approximate timing shown.
STEP
Wakeup event
REGOUT powered
FETs enabled (7 series)
FETs enabled (5 series)
8.2.6 FET Driver Turn-Off
The low-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective
FET. The DSG driver includes an internal switch that drives the DSG pin toward the VSS pin level when the
driver is disabled. The driver is specified with a maximum fall time into a 20-nF capacitive load, with 100-Ω series
resistance between the DSG pin and the DSG gate. If the driver is used with a larger capacitive load, the fall
time generally increases. The system designer can optimize the series resistance value based on the board
components and DSG FET(s) used.
The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the
turn-off transient. A low resistance (such as 100 Ω) provides a fast turn-off during a short circuit event, but this
may result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value
(such as 1 kΩ or 4.7 kΩ) reduces this speed and the corresponding inductive spike level.
The CHG FET driver discharges the CHG pin toward the VSS pin level, but it includes an additional series PFET
to support voltages below VSS. This is generally needed when a pack is heavily discharged, for example, if cells
in a 7-S pack are at 2.5 V per cell, then PACK+ = 17.5 V relative to device VSS. Then if a charger is attached
while the CHG FET is disabled and applies a full charge voltage across PACK+ relative to PACK-, such as 4.3 V
per cell, or 30.1 V for the 7-S pack, this results in PACK- dropping to approximately –12.6 V relative to VSS. To
keep the CHG FET disabled, its gate voltage must drop to near this –12 V level.
To support this type of case, the CHG FET driver in BQ77307 is designed to withstand voltages as low as –25 V
(recommended) relative to the VSS pin voltage by including a series PFET at the pin, with its gate connected to
VSS. When the CHG driver is disabled, the driver pulls the pin voltage downward. As the pin voltage nears VSS,
the PFET is disabled, so the pin becomes high impedance. At this point, the external gate-source resistor on the
CHG FET pulls the pin voltage lower to the PACK– level, keeping the CHG FET disabled.
Oscilloscope captures of the DSG driver turn-off are shown below, with the DSG pin driving the gate of a
CSD18532Q5B NFET, which has a typical C
34
Submit Document Feedback
Table 8-2. Startup Sequence and Timing
COMMENT
Either the TS pin or the VC0 pin is pulled
up, triggering the device to exit SHUTDOWN
mode.
Timing measured with the OTP programmed
to autonomously power the REGOUT LDO.
Timing measured with the OTP programmed
to autonomously enable FETs.
Timing measured with the OTP programmed
to autonomously enable FETs.
of 3900 pF.
iss
Product Folder Links:
APPROXIMATE TIME (RELATIVE TO
Figure 8-5
shows the signals when using a 1.35-kΩ
Copyright © 2023 Texas Instruments Incorporated
BQ77307
www.ti.com
WAKEUP EVENT)
0
2.6 ms
9.4 ms
8.6 ms
Advertisement
Table of Contents
