Achieving Up To Asil-D System Requirements; Static Nvm Settings; Application-Based Configuration Settings - Texas Instruments DRA821 User Manual

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Supporting Functional Safety Systems

4.2 Achieving up to ASIL-D System Requirements

For ASIL-C or ASIL-D systems, there are additional features to the ones described in
utilized. These features include:
PMIC current monitoring on all output power rails
Isolation of the MCU and Main power domains of the processor
SoC reset
The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 and LP8764-Q1
devices. Additionally,
Figure 3-1
resources of the PMICs than the main power domain of the processor. SoC reset functionality is supported
through the connection of GPIO_11 on TPS6594-Q1, configured as nRSTOUT_SoC, to the PORz pin of the
processor.
Residual voltage checking is available on the PMICs to prevent startup when output rails are not
discharged below 100 mV as may happen under a fault condition. However, this feature is not
enabled in the NVM settings of this PDN to support repetitive power cycling during system software
development.

5 Static NVM Settings

The TPS6594-Q1 and LP8764-Q1 devices consist of fixed registers and configurable registers that are loaded
from the NVM. For all NVM registers, the initial NVM settings that load into the registers are provided in this
section. Note that these initial NVM settings can be changed during state transitions, such as moving from
STANDBY to ACTIVE mode. The full register map, including default values of fixed registers, is located in the
corresponding PMIC data sheet. Empty values indicate that the device does not have the register included. For
example, LP8764-Q1 does not have BUCK5 registers at all and therefore the values for it are empty.

5.1 Application-Based Configuration Settings

In the LP876441B1-Q1 and TPS6594141B-Q1 data sheet, there are multiple application-based configurations
for each BUCK to operate within.
10
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
shows that the MCU domain of the processor is powered by different power
Note
Table 5-1
includes the different configurations available:
Copyright © 2022 Texas Instruments Incorporated
Section 4.1
SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022
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