Refresh Memory And Control Logic - Texas Instruments 990 Manual

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CR U Bit Selectors. The CRU bit selectors decode addresses CR, 13-15,B and if enabled by one of
the byte select signals at the S input, pass data (DO through D7) at the selected input to the
computer as CRUBITINT.
1.4.4.5 Refresh Memory and Control Logic. Figure 1-37 is a block diagram of the VDT
controller's refresh memory and associated control and addressing logic.
During a data retrieval (computer writing to CRT) operation, the computer provides the VDT
controller with eight bits of character data over the serial output line (CRUBITOUT). This
information determines what is to be displayed on the CRT screen at the current cursor location
and whether the displayed information is to be displayed normally or at low intensity. The
computer also provides control bits to enable the display and the cursor, and an 11-bit cursor
address over the same serial output data line. The cursor address specifies the position on the
screen where a symbol is to be altered or displayed and the location in the refresh memory
where the information is to be stored. The VDT controller continually reads the contents of
refresh memory and converts the ASCII codes to dot patterns that are sent to the CRT.
After the computer has transmitted the write data and address information to the VDT controller,
the computer issues a Write Data Strobe on the data line (with module select, four-bit CRU
address, and clock). The VDT controller responds by storing the screen data code into its refresh
memory at the cursor address provided by the computer.
During typing operations, when data for display on the screen is repeatedly transferred from the
keyboard to the computer, and then from the computer to the CRT monitor, the computer may
provide the VDT controller with only the initial cursor address. Then, after each character is stored
in refresh memory, an increment command is sent by the computer to update the cursor address.
A counter in the memory control logic performs the incrementing so that all characters are trans-
mitted .in the proper order and stored in refresh memory in consecutive locations. For operations
other than transmission of information for display in consecutive locations, the computer provides
an 11-bit cursor address for each character to be disp!ayed.
The following discussions describe the operation of the circuitry depicted in figure 1-3 7.
Memory/CRU Input Data Register. The memory/CRU input data register consists of two quadruple
two-input multiplexer latch networks that contain the character at the current cursor location
for input to the CRU. Inputs to this register are provided by the computer (CRA,B-7 ,Q) or the
read data latches (MD0,0-7 ,Q).
When a write data strobe occurs, a memory write cycle is initiated. The write data character
(CRA,0-7 ,Q) is selected by the memory /CRU input data register and latched. This data is then
written into memory and is immediately available for input to the computer via the CRU
interface.
When the cursor moves (increment, decrement or load new address), a memory read cycle is
initiated. Memory output data is selected by the memory /CRU input data register and latched.
In this way the register always contains the character stored at the present cursor address.
MID RC is the clock which controls the memory /CRU input data register. When the clock is high,
the register output tracks the selected input, and the output is latched when the high-to-low
transition occurs.
1-59
Digital Systems Division