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General Description
1.5.2.4
Scratch Pad RAM.
During self-test, the 990/10A requires scratch pad memory area for use
as workspace registers, temporary storage, etc. Therefore, a 128 x 16 random-access memory (RAM)
is implemented which can be accessed during self-test only. To use the scratch pad RAM, a latch
must be set by writing a one to bit two of the diagnostic register (CRU address > FAFE). After that,
any
subsequent
access
to logical
memory
address
>FAOO
through
>FAFF
is directed
to the
scratch pad RAM. The scratch pad RAM
is disabled by writing a zero to bit two. The scratch pad
RAM is not accessible from the TILINE.
1.5.2.5
Loader/Self-Test ROM Mapping.
The loader/self-test read-only memory (ROM) contains a
total of eight kilobytes
of loader/self-test code. The 990/10A has the capability to directly access
one kilobyte of ROM
code only. Therefore, the 990/10A uses an addressing scheme that is com-
patible with the 990/12 to allow the access of an additional seven kilobytes of loader/self-test code.
This is accomplished by dividing the loader/self-test ROM into eight pages, with each page contain-
ing one kilobyte. From Table 1-2, note that one kilobyte is the total allowed by the address alloca-
tion. The
page
that
is being
addressed
is then
determined
by three
latched
bits written
into a
register at memory address >FAFE,
not by the address field. This address normally is within the
TPCS and initiates a TILINE cycle. Therefore, the ROM page address field is qualified to be acces-
sible only when the scratch pad RAM
is enabled. The ROM
page address field then appears as the
last word of the scratch pad RAM
memory space (>FA00 — >FAFE). On power-up, loader self-test
page zero is selected. The page selected is changed by setting the scratch pad RAM enable bit at
CRU address >FAFE bit 2 and then writing to bits 13, 14, and 15 of memory address >FAFE. The
transition from page to page is based on the principle that the microprocessor prefetches the next
instruction before accomplishing the destination write from the present instruction. An example
instruction sequence
follows:
LI
R5,@ NPEP
LOAD NEW PAGE ENTRY POINT
INC
R4
INCREMENT PAGE COUNTER
MOV
R4,> FAFE
PERFORM THE PAGE SWAP AFTER PREFETCH
B
*R5
BRANCH TO ENTRY POINT
1.5.3
Memory Correction and Control
The correction and control chip is a custom LSI integrated circuit that performs the error detection
and correction
algorithm employed
on other 990 memory
products. This chip generates
a six-bit
checkword with each memory write. On subsequent memory reads, the checkword is used to correct
single-bit errors and to flag double-bit errors. The error condition of all logic ones or all logic zeros
from memory
is detected, but other errors of three or more bits may
not be detected. An on-chip
register that responds
to a TPCS
address
permits control of the error-correcting
function
for
diagnostic purposes. The error correction can be disabled to certain rows of memory chips, or the
checkword can be interchanged with the six most significant bits (MSBs) of the data word to verify
the cause of a failing condition. Status information about the test results, memory size, memory ad-
dress, and'chip-in-error can be read through two 16-bit registers (the memory error log) in the TPCS
whose address is selected by pencil switches on the 990/10A board.
The correction and control chip also includes two addressable registers for controlling interrupts
among
processors in a multiprocessor system whose addresses are also switch selectable.
2302633-9701
1-9
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