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990/10A
Manual
Texas Instruments 990/10A Manual
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Contents
Table of Contents
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Table of Contents
Table of Contents
General
Purpose of Equipment
Equipment Description
Microprocessor
Memory
Asynchronous Communication Controller
Memory Mapping
Map Operation
Map Initialization
TILINE Peripheral Control Space (TPCS) Mapping
Scratch Pad RAM
Loader/Self-Test ROM Mapping
Memory Correction and Control
Memory Allocation
Interrupts
Level 0 Interrupt (Power Restored)
Level 1 Interrupt (Power Failure Imminent)
Level 2 Interrupt (Error Conditions)
Level 3 Host Processor Interrupt
Level 5 or 15 Interrupt (Real-Time Clock)
Level 8 (EIA Port Interrupt)
External Interrupts
Nonmaskable Interrupt (NMI)
Communication Register Unit (CRU) Controller
Parallel CRU Operations
CRU Addressing
Backpanel Interface
Front Panel Interface
Asynchronous Communication Port
TILINE Interface
Tiline
TILINE Slave
TILINE Hold
TILINE Wait
General
Unpacking/Packing 990/10A Board
990/10A Installation Procedures
Setting Option Switches and Jumpers on the 990/10A Board
Operation
General
Control/Display Module Controls and Indicators
Controls
RUN Switch
HALT Switch
ALT LOAD Switch
Indicators
Hexadecimal Display
Powerled
Faultled
Runled
Idleled
990/10A PWB Indicators
Major Fault LED
Fault LED "0
Memory Error Indicators
Double-Bit Error
Single-Bit Error
Bit-In-Error
Self-Test Description
Major Fault Test
General Fault Test
Self-Test Execution Time
Self-Test Error Reporting
Bypassing a Self-Test Failure
Other Information Available as a Result of a Self-Test Failure
Load Device Verification
Special Features of Load Device Verification
Understanding Self-Test Error Codes
Understanding Loader Error Codes
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MODEL 990/10A COMPUTER
GENERAL DESCRIPTION
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