Texas Instruments 990 Manual page 49

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945424-9701
1.4.2.1 Buffer Register. The buffer register is an eight-bit flip-flop register that latches the eight-bit
keyboard data code, KBDT,1-8, when strobed by Keyboard Data Strobe (KBSIN-) and holds
the latched keyboard code for the UART transmitter until a new data code is transmitted by the
keyboard. The buffer register always contains the last character code transmitted by the
keyboard.
1.4.2.2 UART Transmitter. The UART transmitter is the transmitter portion of a universal
asynchronous receiver/transmitter. The transmitter accepts the parallel eight-bit output of the
buffer register when loaded by TBRLD-. The transmitter latches the eight-bit code, adds one
start bit, one parity bit, and one stop bit, and serializes the "assembled" 11-bit code, clocking
the data out at the rate of one bit for each 16 clocks. The serial 11-bit code is driven out to the
VDT controller on a pair of lines and provided to the serial input of the UART receiver. The
UART receiver output drives a LED display for operator monitoring of keyboard operation.
The frequency of the output of the H-Sync generator is 15. 72 kilohertz, so the character output
rate of the UART transmitter is 89.3 characters per second (16 clocking pulses are required for
each bit converted from parallel to serial format by the UART transmitter). Figure 1-23
illustrates the timing relationships for the UART transmitter.
Each time the UART transmitter transmits a character, the transmitter produces a signal,
TREMPTY, that enables the transmitter to accept a new data code from the buff er register.
During character transmission, TREMPTY is held low to disable the acceptance of a new code
from the buffer register.
1.4.2.3 UART Receiver. The receiver portion of the UART monitors the ! I-bit serial output of
the UART transmitter, removes the start and stop hits, converts the remaining nine bits into a
parallel code identical to the eight-bit code received from the keyboard, and provides a parity test
flag bit. These nine outputs of the UART receiver are used to drive the LED display to allow
visual monitoring of the last code received from the keyboard and a parity indication.
1.4.2.4 LED Display. The LED display consists of 10 LEDs that indicate the status of each of
the eight keyboard data bits, the parity bit, and the presence or absence of horizontal sync pulses.
Figure 1-24 illustrates the LED display which
ls
located on the rear of the display unit cabinet.
For the keyboard data bits, a lighted LED indicates a logic 1. The parity (P) LED is normally
lighted and indicates that the parity of the last character transmitted by the UART was correct.
The Sync (S) LED should always be lighted during normal operation of the terminal to indicate
the presence of horizontal synchronization pulses from the VDT controller.
1.4.2.5 Repeat Logic. The repeat logic on the power/logic pwb produces the pulses that load
the outputs of the buffer register into the UART transmitter. The repeat logic produces one
pulse (TBRLD-) to load the transmitter each time a data key is struck without the REPEAT
key actuated, or produces I 0
±
2 pulses (TBRLD-) per second whenever a data key is struck
while the REPEAT key is being held down. The repeat circuit is illustrated in figure 1-25.
The primary component of the repeat circuit is a timer biased for astable oscillation at 1 O
±
2
hertz. The remainder of the circuit enables the timer whenever a data key is struck, either alone
or with the REPEAT key, and disables the timer all the rest of the time.
Whenever a data key is struck, KBSIN- sets the strobe flip-flop and enables the timer. The timer
produces a high-active output that loads the UART transmitter (drives TBRLD- low) if the
transmitter is empty (TREMPTY
=
l ).
1-39
Digital Systems Division