Texas Instruments 990 Manual page 50

~~--94_5_4_24_-9_1_0_1
__________________________________
~----------
TBRLD-
OUTPUT
TR EMPTY
(A )1 36273
NOTE 3
--+I I+--
NOTE 2
I I .--;--;--;--;--;--;-I
tl.' I
I
I
I
•
W I I I I I
I
I
START DATA!
_J
DATA8 PARITY STOP
. I
·-~-~- -~-~-~-~
lc:;TART
1
I
L.:.J -
_J
-+I
l~NoTE;
----i~·------~----~------------------------~-11_2_c_L_oc_K
__ cy_c_L_E_--+ ____
I+-- __ __
NOTES: 1. BIT TIME IS 16 CLOCK CYCLES•
2. IF TRANSMITTER IS INACTIVE, THE START PULSE WILL APPEAR ON LINE WITHIN ONE
CLOCK CYCLE OF TIME DATA STROBE OCCURS (SEE DETAIL BELOW).
3.
2~$¢..~i~rl'bi~1~dVrf~~i., ?~~.~'NE o~u~~f~fgtE~N?:HER
DATA STROBE CAN OCCUR
TBRLD-
I
--+I I+---
1/16 BIT
CLOCK
Lflilil_
uuTPu
1
Figure 1-23. Model 911 VDT Power/Logic PWB UART Transmitter Timing Diagram
NOT PART OF CHARACTER
TRANSMISSION MONITOR
!
oeeooooeee
8
7
6
5 4 3
2
p
s
(A)136274
NOTE:
e
LIGHTED LED
Figure 1-24. Model 911 VDT LED Display
If the REPEAT key is not held down (REPEAT-
=
1 ), the trailing edge of the timer's
high-active output resets the repeat flip-flop and, in tum, resets the strobe flip-flop and disables
the timer before a second output pulse can be produced.
If the data key is struck while the REPEAT key is held down, KBSIN- sets the strobe flip-flop
and enables the timer. Since REPEAT- is held low, the timer's output does not reset the repeat
flip-flop, and the timer produces outputs at 10 ± 2 hertz as long as the REPEAT key is held
down. Since the UART transmitter empties itself at a faster rate than the repeat circuit produces
loading pulses, TREMPTY is always logic 1 prior to each timer output pulse during the repeat
operation. Therefore, TBRLD- oscillates at 10 ± 2 hertz (the timer circuit rate) and causes the
character code being held by the buffer register to be repeated.
1-40
Digital Systems Division